Recent years have witnessed a significant interest in the “generative adversarial networks” (GANs) due to their ability to generate high-fidelity data. GANs have a high compute and memory requirements. Also, since they involve both convolution and deconvolution operation, they do not map well to the conventional accelerators designed for convolution operations. Evidently, there is a need of customized accelerators for achieving high efficiency with GANs.
We present a survey of techniques and architectures for accelerating GANs. We review accelerators based on in-memory computing using ReRAM and SOT-RAM and those implemented on FPGA and ASICs. We discuss various optimization techniques for GANs, such as Winograd-based CONV, sparsity-related optimizations, etc. Paper accepted in Journal of Systems Architecture 2021. Available here.
We present a survey of techniques and architectures for accelerating GANs. We review accelerators based on in-memory computing using ReRAM and SOT-RAM and those implemented on FPGA and ASICs. We discuss various optimization techniques for GANs, such as Winograd-based CONV, sparsity-related optimizations, etc. Paper accepted in Journal of Systems Architecture 2021. Available here.