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In the 1980's you could buy HSPICE from Meta Software and simulate your custom IC or ASIC with confidence. Today we have so many more choices.
This is the place to discuss all things SPICE, Fast SPICE and Analog Fast SPICE.
SPICE (Simulation Program with Integrated Circuit Emphasis) is used today by IC designers for custom and analog IC designs who need the highest accuracy.
Fast SPICE is like SPICE by reading a transistor-level netilst however it runs much faster by making assumptions about your circuit netlist and will partition the netlist automatically into smaller pieces which can then be solved more quickly. Fast SPICE simulators can be either flat or hierarchical tools.
Analog Fast SPICE is a phrase coined by Berkeley Design Automation and creates a category in between SPICE and Fast SPICE. No partitioning is done with Analog Fast SPICE and yet it is about 5X faster than traditional SPICE.
With multi-core CPUs in common use the challenge has been to adapt the SPICE algorithms to utilize all cores during simulation, thus speeding up the results.
I'd be interested to see actual benchmark times/accuracy reports. What is "traditional SPICE", if it's Spice 3 from Berkeley then everything is faster than that, and it's decades old so that's no surprise. And what does "analog fast spice" mean vs anything else?
Whatever technology you use for simulation, if you are creating the next generation of hardware, then you always lose on the dimensions of complexity and scale, so no matter how fast your transistor level simulation at some point it's just not fast enough. At some point you have to abandon transistors and move up into behavioral modeling.
Also, given the high variance in actual Silicon behavior in sub 45nm designs, large scale spice simulations that are not able to include that variability in behavior (aka Multi-mode/multi-corner), are not very useful, and if you have to run lots of corners then parallel processing doesn't help (Amdahls law).
When I marketed a FastSPICE tool at Mentor for 6 years we saw IC designers extensively benchmark our simulator versus HSPICE, NanoSim, HSIM, etc. They often would evaluate the tool for 3 months to 6 months in order to build trust in the simulation results over hundreds of different netlists they had designed.
Traditional SPICE is a circuit simulator that builds one matrix to solve for current and voltage as a function of time.
Fast SPICE simulators partition the netlist into smaller pieces and each piece goes into a small matrix, instead of a single large matrix.
Analog FastSPICE is SPICE but with improved speed and still a single matrix.
Yes, you can never have a SPICE simulator run fast enough so it does make sense to use FastSPICE and AMS simulators where you can mix SPICE with language-based models.
Agreed on the sub 45nm designs the number of simulation corners has exploded and it's clear to me that the variation within a die is a greater percentage number than the accuracy of the SPICE simulation tool.
Just curious about the kind of work that you do now. You can send me a private message if you like.
There is never enough speed in a simulator ... just as the simulator advances, so does the device model complexity. Then comes parasitic extraction ... and to make matters worse, you can even do parasitic inductance as well these days !
This is the "art of analogue design" ... trading off speed for accuracy "at the right places" ...
I remember in the early days of FastSPICE circuit simulators, you could always kill simulation speed by adding one inductor in the Power/Ground network or simply add a bipolar transistor.
On the speed of circuit simulation, why don't we see more uses of GPU or special purpose co-accelerators to make SPICE run faster? Couldn't someone design a dedicated CPU just for floating point matrix operations?
I successfully used Cadence UltraSim for debugging an SRAM block. It is a pitty though it is not multi-threaded at the moment. One of the most difficult things is to manage the risk in the time versus accuracy tuning. You know it did run fast but you don't know if it was accurate enough.
Staf,
MT code requires a major re-write so EDA management balks at the effort required. To be competitive all SPICE tools will become MT.
About the accuracy, we used to call our competitor tools, "Fast with wrong answers".
In the old days for simulating memory like SRAM and DRAM we would cut out a netlist only of what we perceived to be the critical path so that it could fit into a SPICE simulator.
Staf,
In the old days for simulating memory like SRAM and DRAM we would cut out a netlist only of what we perceived to be the critical path so that it could fit into a SPICE simulator.
I know, people overhere call it a doughnut. The problem I was debugging was only happening post-layout; making a doughnut after parasitic extraction seemed a lot of work to me also.
