[content] => 
    [params] => Array
            [0] => /forum/index.php?threads/sondrel-builds-on-7nm-design-work-to-offer-5nm.13715/

    [addOns] => Array
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2020771
            [XFI] => 1050170

    [wordpress] => /var/www/html

Sondrel builds on 7nm design work to offer 5nm

Daniel Nenni

Staff member
Reading, UK 3 February 2021. As more and more foundries are offering 5nm, Sondrel has announced that it is supporting them with 5nm design work. This builds on it being one of the few design houses to have taped out a number of 7nm designs.

Graham Curren, Sondrel’s CEO and Founder, said, “We are one of the few design companies working on Samsung and TSMC at these advanced nodes. Firstly, because they are invariably extremely large and complex with billions of gates in a design, which requires a large team of extremely experienced design engineers. For example, we recently finished a design on 16nm that required over a hundred people working on it full time for over a year; a resource deployment that would typically only be available within a big Blue-Chip company. Secondly, we have expertise from several designs at 7nm that gives us a head start on the learning curve of understanding the requirements of 5nm.”

The key driving force to move to the 5nm node is the increase in performance due to the smaller distances increasing the operational speeds. For these leading-edge chips, this increase in performance can justify moving to a smaller node, especially alongside the decreased unit cost associated with reduction in the silicon real estate and the power demand being less for the same functionality.

An example of the design intricacies of these ultra-small nodes that needs to be understood and allowed for is that the resistance of the metal layers varies from the lower to the upper. In an ideal design, the lower, thinner layers with the higher resistance are used for local/short connections and the mid and high levels for longer distances. However, in the real world, there can be areas of congestion where all the high, fast levels are already fully utilised forcing the tool to use the lower slower layers, causing timing closure issues that have to be addressed in the design.

About Sondrel™
Founded in 2002, Sondrel is the trusted partner of choice for handling every stage of an IC's creation. Its award-winning define and design ASIC consulting capability is fully complemented by its turnkey services to transform designs into tested, volume-packaged silicon chips. This single point of contact for the entire supply chain process ensures low risk and faster times to market. Headquartered in the UK, Sondrel supports customers around the world via its offices in China, India, France, Morocco and North America. For more information, visit

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