Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/shrink-slows-speed-accerates-moores-law-dying.8493/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021370
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

Shrink Slows, Speed Accerates, Moore's Law Dying

Arthur Hanson

Well-known member
Moore's law is reaching its end game, but speed isn't. New materials hold the promise of much faster speeds that will accomplish the same effective results as shrink. Also new types of memory will be key to the game. In the not to distant future, between the increase in power from speed and greater on board memory mobile devices will have near AI capability. This tied in with very sophisticated, rapidly shrinking sensors will provide the next frontier for the semi conductor industry. It will be interesting to see how Semi companies make the transition. The dropping costs and increased performance will provide a constant source of new uses and applications for semis with its only limits being our imagination. One thing we have seen the semi sector do over the last fifty years is to constantly adapt and find new frontiers. Anyone who thinks this will stop or even slow down, needs to think again. Comments and thoughts solicited and welcome.
 
Is there any update on cost per transistor for 14/16nm, 10nm and 7nm? Last time this topic was discussed in depth at semiwiki (that I remember), Intel was just beginning HVM of 14nm and TSMC and Samsung still had no 14/16nm silicon shipped.

I remember that some said 28nm would be the cheapest and, beyond that, all smaller nodes would either maintain or slightly increase cost per transistor.

What is the current status as far as cost per transistor goes?

About new materials, is there anything in the pipeline that we could see reaching market in the next 3 years? What is it, who is leading it and what are the pros and cons of such developments?
 
Last edited:
There are a number of new materials on the horizon and 2D structures should be coming out soon. Google both, for both of these subjects require more depth than time permits.
 
About new materials, is there anything in the pipeline that we could see reaching market in the next 3 years? What is it, who is leading it and what are the pros and cons of such developments?

The natural progression from FinFET will be the lateral, gate-all-around nanowire structure -- in Silicon.

Carrier confinement would be sufficiently strong in this structure that you could really consider it a new (1-D) material system.

After this, materials options for pFET devices include Ge or SiGe, and maybe a III-V material for nFET.

The timing of developments is perhaps impossible to predict, but I'm sure that Arthur is basically correct.
 
Low power needs complimentary transistors (n & p) unless you can find a way to do some asynchronous logic with charge storage that doesn't require power to hold state. Speed is overrated, power is more important if scaling has stopped since you want to die-stack to get better system density - gates/m^3 rather than gates/m^2.

Smart 3-D DRAM next?
 
Back
Top