I think maybe you swapped CGP and MMP at some points? If they can leverage CGP they might shrink earlier but there's always density vs. performance tradeoff.
yeah you are right. i corrected them.
Yes, I was speaking of performance versus density. Remember, Samsung 14nm was not designed for AMD. It was originally designed for SoCs from QCOM and Apple. I can assure you that AMD is the first silicon to go through GF 7nm. It really is exciting!
I'm not convinced EUV will help 7nm with 5nm so close behind.
The other interesting thing is the IBM version of 7nm and 5nm. GF 7nm looks more like TSMC 7nm than the IBM 7nm chip. I guess GF learned what not to do from IBM?
EUV will definitely help 7nm with improved transistor density, reduced defect density and lower cycle times. Gary Patton talked in one of his interviews about how EUV would benefit 7nm
Semiconductor Engineering .:. To 7nm And Beyond -Semiconductor Engineering
Patton: There are projections that 7nm is going to be in the 80-mask range. People think about
EUV for scaling, but at least in the initial phase the
cycle-time improvement will be a great benefit. To be able to go from
80-plus masks down to 60-plus masks would be a huge benefit. Add to that the
defect density benefit, because you’re not depositing and etching and running all these process steps that add defects to the wafers.
Caulfield: Even with 14/16nm technologies, the number of mask steps are in the low 60s.
You can do some of the lower-order thin wire quad patterning, cut masks steps out, and all of a sudden you’re doing the same number of mask steps at 7nm.
AMD already confirmed Zen 3 on their roadmap at 7nm+ which is probably an improved 7LP with EUV and even better performance. One more thing is that I do not see GF developing half nodes(as their main customers IBM/AMD are high performance and not mobile) so their next node whatever its called (5nm or 4nm) would probably launch in 2021 with actual products shipping in early 2022. I think that a full node jump with >30% transistor perf increase and >2x transistor density improvement will take 3 years. I don't know if TSMC 5nm is a node like 10nm with 2x transistor density improvements but with transistor perf increase of 15% (which is more like a half node). Gary Patton also mentioned the same about what the 5nm node is going to mean
Semiconductor Engineering .:. To 7nm And Beyond -Semiconductor Engineering
Patton: It’s too early to tell, but it looks challenging. That may mean it takes longer to get to a true 5nm. If it has to have EUV, and it has to have new device structures, it will take a long time.
7nm will be a long node in my view. There will be performance tweaks on it.
Caulfield: But here is what the industry is learning: If a design is going to cost $300 million to $500 million, it better have real value. With 20nm, there were two high-volume chips, but the rest of the industry saw that as a failure. Every node will be defined. With 7nm, if you shrink 65% you can get a real cost savings. Complexity goes up, so maybe you don’t get the full savings, but you get a portion of that, and you get performance. We believe 10nm will be a few companies looking for performance to hit a market, and everyone else will wait for 7nm.
Patton: 20nm was a misstep in my opinion. It was improved with a 14/16nm finFET, but it was really a 20nm process. 10nm was another misstep. There is not a huge value proposition in terms of performance. With local layout effects, they’re getting very little performance improvement. There is a power benefit, but very little in terms of performance or cost.
If people rush to 5nm, it could be a repeat of 10. If we take our time and really define the node, then it could be a good technology node.
