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Samsung to share node information at VLSI symposium.

2 years behind in 4nm, 1 year behind in 3nm. Five years to catch up.
I wonder where the inspiration for that came from :ROFLMAO:

On an actually constructive note I think I mostly agree with their assessment of how their current technology matches up. With the caveat that 3GAP is one year behind TSMC and it has to be a real node in real products anyone can buy (not in a couple of galaxies in Europe like 4LPE is right now).

I also think that this announcement would be more believable and better received if we saw 4LPE in a similar situation to intel 10nm back in early 2021 when we saw intel accelerated (icelake u in good volumes, tigerlake u/h in huge volumes and finally being objectively better than all 14nm mobile parts, and icelake server parts). Lastly I think Samsung needed more details on their roadmap for us to access the feasibility and benchmark their progress over the years. I saw on their roadmap 1.4 was a different color that 3 and 2. Is this just for the looks like 4 being a different color from 5 and 7? Or does Samsung think they are doing CFETs in 2027. These sort of details as well as PPA or density targets would add credibility to this statement.

Hopefully we get charts with labeled axis so I can update my “3nm” performance post.

On a somewhat related note I’m sad to see that there doesn’t seem to be a paper for intel 3 at the conference. Just the derisk node for backside power (which will no doubt be an interesting read in its own right). I just hope intel 3 eventually gets a wonderful paper like intel 4 did, we get to see how the new libraries compares to the i4 HP, and all of their intel 7 equivalents (ideally both the 54 and 60nm gate pitches but I’m okay if for simplicity sake they just do the 60nm versions). If instead we get a marketing announcement like for 10nm SF, I will be somewhat disappointed with intel.
 
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