I'm not saying there is stuff they want secret. Ideally everything is secret from x fab operator's perspective. However if an issue was solved by a vendor, then you can take it to the bank they will use it to help their other customers within the confines of not breaking their confidentiality agreements with said customer. Add-ons and modifications are also totally fair game to send to other operator's given that is 100% vendor IP (even if it was a request from some operator).
Samsung 3nm GAA process first look with Whatsminer ASIC (TechInsights)
- Thread starter Fred Chen
- Start date
TSMC also leads in power reduction which is a big deal for mobile SoCs. It seems to me that TSMC could do very high performance if they wanted to but maybe customers have not required it? Maybe TSMC will change that with the AI and HPC bubble?
Some inputs:
1. During COVID, due to experts were hard to travel, AR/Hololens technology was adopted for tool installation and troubleshooting in equipment vendors included ASML, Lam and more. The installation and tool fixing effectiveness seems improved.
2. If one customer purchased ~50% of ASML EUV tools and it expects to be the same in the near future. Will any vendor treat his big customer without providing major resources to help customers's success, but bet on some emerging/potential big customer? There should be some very solid reasons like big volume committed and very good margin for big order, or others. Does Intel or Samsung fit?
3. tsmc claimed in his technology symposium that he had 50% of WW EUV tools and delivered 60% of WW EUV output wafers. If we roughly estimate, this implies tsmc's wafer output per tool is 50% more than other 50% tools.
4. I remembered ASML's service contract for EUV is counted by wafer output, not traditional annual rate base. If ASML leads EUV HVM, wants to earn more service fee, then it makes sense to help his other customers to output more wafers and makes more money. But the wafer output between customers seems not fit the wish well.
5. To make EUV HVM be successful, tool is very critical. But we also know the suitable photoresist can help on dose reduction(wafer more output ==>$$ saving) and better metrology and process control also play roles. These could be integrated by manufacturers like tsmc, Samsung or intel, but not dominated by ASML. ASML owns tool IPs but not process IP.
6. For HPC chip which typically is big die(>500mm2, even up to 800mm2), the most critical part will be how many good dies can be delivered in one wafer. Defect density reduction could be more important than cost reduction(EUV dose reduction). Even EUV pellicle(consumed EUV power) might be implemented to help wafer yield. The contribution from ASML in this part(process) will be very limited also. For ASML next generation EUV tool with higher output power, higher throughput at the same dose and better MM matching, it definitely will help deliver more HPC chips.
7. Chiplet technology could be a destructive innovation for technology leader with higher yield in the most advanced nodes and could impact Hi NA EUV adoption.
1. During COVID, due to experts were hard to travel, AR/Hololens technology was adopted for tool installation and troubleshooting in equipment vendors included ASML, Lam and more. The installation and tool fixing effectiveness seems improved.
2. If one customer purchased ~50% of ASML EUV tools and it expects to be the same in the near future. Will any vendor treat his big customer without providing major resources to help customers's success, but bet on some emerging/potential big customer? There should be some very solid reasons like big volume committed and very good margin for big order, or others. Does Intel or Samsung fit?
3. tsmc claimed in his technology symposium that he had 50% of WW EUV tools and delivered 60% of WW EUV output wafers. If we roughly estimate, this implies tsmc's wafer output per tool is 50% more than other 50% tools.
4. I remembered ASML's service contract for EUV is counted by wafer output, not traditional annual rate base. If ASML leads EUV HVM, wants to earn more service fee, then it makes sense to help his other customers to output more wafers and makes more money. But the wafer output between customers seems not fit the wish well.
5. To make EUV HVM be successful, tool is very critical. But we also know the suitable photoresist can help on dose reduction(wafer more output ==>$$ saving) and better metrology and process control also play roles. These could be integrated by manufacturers like tsmc, Samsung or intel, but not dominated by ASML. ASML owns tool IPs but not process IP.
6. For HPC chip which typically is big die(>500mm2, even up to 800mm2), the most critical part will be how many good dies can be delivered in one wafer. Defect density reduction could be more important than cost reduction(EUV dose reduction). Even EUV pellicle(consumed EUV power) might be implemented to help wafer yield. The contribution from ASML in this part(process) will be very limited also. For ASML next generation EUV tool with higher output power, higher throughput at the same dose and better MM matching, it definitely will help deliver more HPC chips.
7. Chiplet technology could be a destructive innovation for technology leader with higher yield in the most advanced nodes and could impact Hi NA EUV adoption.
Realizing this, customers wouldn't make their vendor deliver the final setup for yield targets.
Do you mean it's a threat to current leader TSMC?
So clearly, I don't expect TSMC to inform ASML what resists they use.