Daniel Payne
Moderator
Abstract—Design of custom integrated circuits hasbecome prohibitively expensive for many applicationdomains. As a result, these domains often choose toimplement the desired functionality on programmableplatforms, but those solutions are less energy efficient.This paper proposes several approaches for making thedesign process more efficient and enabling custom energyefficientintegrated circuits. Function generators, asopposed to function instances, should be designed, whichcombined with higher-level design abstraction improvedesign efficiency and foster reuse. The use of generatorsalso enables modular designs, aiding design verification.Rapid design flow maps generated modules into siliconand enables design-space exploration for optimalefficiency. Open-source repository of function generatorsand their mappings into systems allow designers toselectively add value to the design. These principles aredemonstrated on a design of a processor, based on anopen-source instruction set architecture, with integratedswitched-capacitor DC-DC converters implemented in28nm FDSOI. The chip is designed with a relatively smallteam and features high conversion efficiency (80-86%) andhigh energy efficiency (26.2 DP GFLOPS/W).
Bernard Murphy
Moderator
This is an interesting idea, especially for FPGA where you want ultra-low cost but still reasonable power efficiency. I see a problem though for semi-custom implementations. Open-source IP is of course appealing but the risk/reward tradeoff doesn't work, at least today. We want this stuff to be free, or close to free, but we also want it to be zero risk because we're going to commit significant NRE to building the silicon. I don't see an easy way out of that trap today other than to embed programmable logic in an otherwise standard architecture. Then any risk is mitigated by being able to change logic without an NRE hit. But that doesn't work for something that has to be high-performance/low power. Catch-22.
If the IP could be well-proven in advance somehow, that might work. Say Kickstarter projects to fund multi-project wafers for an open-source validation group? (I have see Kickstarter used to fund free-access music projects)
If the IP could be well-proven in advance somehow, that might work. Say Kickstarter projects to fund multi-project wafers for an open-source validation group? (I have see Kickstarter used to fund free-access music projects)
I
ippisl
Guest
>> If the IP could be well-proven in advance somehow, that might work. Say Kickstarter projects to fund multi-project wafers for an open-source validation group?
That could work , but making each fix via a new MPW, might be a bit expensive. In that spirit , i can imagine some kind of arduino , designed in the name of open-source , with open-source peripherals , on an fpga and sold as an arduino board - to create excitement among the community(both for openness , as a great learning tool for the whole system, and creating possibilities for projects) . And the community, by using those peripherals - will find the bugs and the corner cases, and report them(or solve them, if they enjoy that, want to learn, etc) - and in return they'll get an update for their FPGA. Plus more test cases will be added to the IP.
And once everything stabilizes , an MPW would be in order.
BTW , there's already a project[1] that builds an arduino fpga , with the goal of code acceleration and improved peripherals , while staying code compatible with the arduino ecosystem. But it doesn't use APB and the fpga is closed.
[1]http://makezine.com/2015/11/17/xlr8-project-blends-fpga-speed-arduino-coding/
That could work , but making each fix via a new MPW, might be a bit expensive. In that spirit , i can imagine some kind of arduino , designed in the name of open-source , with open-source peripherals , on an fpga and sold as an arduino board - to create excitement among the community(both for openness , as a great learning tool for the whole system, and creating possibilities for projects) . And the community, by using those peripherals - will find the bugs and the corner cases, and report them(or solve them, if they enjoy that, want to learn, etc) - and in return they'll get an update for their FPGA. Plus more test cases will be added to the IP.
And once everything stabilizes , an MPW would be in order.
BTW , there's already a project[1] that builds an arduino fpga , with the goal of code acceleration and improved peripherals , while staying code compatible with the arduino ecosystem. But it doesn't use APB and the fpga is closed.
[1]http://makezine.com/2015/11/17/xlr8-project-blends-fpga-speed-arduino-coding/
I
ippisl
Guest
Ah sorry Bernard, forgot to ask - do you think that such open-source verification methodology like i posted in the previous comment ,could work well ?
Bernard Murphy
Moderator
Hi ippisi - I think it's an interesting idea. There's an element that is difficult to predict - viral uptake and growth of a movement around the idea. Attaching to the Maker movement would certainly help - to the extent anything has the power to go viral, that certainly does. And I would expect Arduino-like platforms to be a big part of maker needs around electronics. But how much will makers want to dig into hardware versus software on those platforms? They'll definitely want standard interfaces so that much is good for free or very cheap IP in those areas, but that would be a limited set. Again, my crystal ball is not so good in this respect. Arduino is good, maker movement is good, FPGA-based Arduino seems good, rest I can't see that far 
I
ippisl
Guest
Thanks Bernard.