Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/report-google-to-switch-from-samsung-to-tsmc.20583/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021370
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

Report: Google to switch from Samsung to TSMC

Fred Chen

Moderator

According to a new report, Google’s work on moving Tensor G5 production to TSMC is nearing finalization for the design in a major step towards production.

Google’s Tensor chips have, so far, been produced through Samsung. Google built on an Exynos foundation for its first few chips, with mixed results. Tensor G3 has been the first release that’s held up well over time, but it was reported last year that Google had plans to introduce its own fully custom chip in the future. That chip would be produced by TSMC and used in the Pixel 10 series in 2025.

Since that initial report, Google has reportedly worked out testing for the chip and evidence of the company’s plans showed up publicly too. It was also reported last month that, unsurprisingly, the chip would be produced on TSMC’s 3nm process.

Now, a new report out of Taiwan from Commerical Times says that Google has reached the “tapeout” stage of development on Tensor G5 at TSMC. This stage is a major step towards production, and considered a tipping point for the design. As Wevolver explains, the “tapeout” stage marks the point at which the design is finalized and the chip moves from development to production. It’s a critical phase for any chip, and is really the decision-maker for whether or not a chip will be made.

While Google isn’t expected to ship anything with Tensor G5 for over a year, the timeline here makes perfect sense. Chip design is a long process, and having things moving towards finalization a year ahead of time means Google is probably right on schedule.

This latest report came out at the end of June, but there haven’t been any updates just yet on how this last step has progressed (though the publication reiterated the status in another post yesterday).

Meanwhile, Google is set to launch the Pixel 9 series very early, with the company hosting a launch event on August 13.
 
So who will get short shrift following the Google move , somebody losing out on something at TSMC whether it be volume or cycletime surely
 
So who will get short shrift following the Google move , somebody losing out on something at TSMC whether it be volume or cycletime surely
Google's order is very small in tsmc so it should not impact other customers' volume/cycle time.
 
Google's order is very small in tsmc so it should not impact other customers' volume/cycle time.
This is 100% correct and is a major TSMC strength. Example: Google could double its orders on that product and TSMC could fit it in (if they wanted) without much impact. TSMC is running 15x the number of production (Selling for revenue) 3nm wafers as Intel is in its Fabs (D1x and Fab34)
 
Google signed that N3 wafer deal with TSMC a long time ago. Google also used TSMC N5 for TPU. If I remember correctly Samsung was 7nm. But true, not big volumes at all. The rumor I heard is that Google has the TSMC N2 PDK so they will stay with TSMC.
 
Google signed that N3 wafer deal with TSMC a long time ago. Google also used TSMC N5 for TPU. If I remember correctly Samsung was 7nm. But true, not big volumes at all. The rumor I heard is that Google has the TSMC N2 PDK so they will stay with TSMC.
Interesting story here (from 2023): https://www.androidauthority.com/google-tensor-g4-pixel-9-3363795/

As reported by The Information (paywalled), Google initially planned to release its 2024 Pixel series with a “fully custom” Tensor SoC codename “Redondo” (internally also known as “RDO”), built on a TSMC process node. However, due to a missed deadline, the chip was too late to be included in 2024’s Pixel 9 series (as chip development is a lengthy process, usually starting years before release).

Google has instead decided to manufacture the SoC for testing purposes, as its successor, which will likely make it into the 2025 Pixel devices, will share many of its design elements. As we’ve learned, Google has designed a development board called “ChallengerDeep” to work on the chip.

There is, however, still the matter of Pixel 9. With Redondo out of the picture, Google needs another chip to become the Tensor G4. The solution to this problem is a new chip codenamed “Zuma Pro.” Note that the Tensor G3 — the SoC that’s coming to the Pixel 8 series — is known as “Zuma.”

The new chip is still semi-custom, co-designed with Samsung’s System LSI division, and will most likely be a smaller upgrade than initially planned. This is similar to how Tensor G2 (codename “Whitechapel Pro”) was a modest update over the original Tensor (“Whitechapel”). The chip currently runs under a development board codename “Ripcurrent 24” (also referred to as “Ripcurrent Pro”), whereas the Tensor G3 used just “Ripcurrent”.
 
Interesting story here (from 2023): https://www.androidauthority.com/google-tensor-g4-pixel-9-3363795/

As reported by The Information (paywalled), Google initially planned to release its 2024 Pixel series with a “fully custom” Tensor SoC codename “Redondo” (internally also known as “RDO”), built on a TSMC process node. However, due to a missed deadline, the chip was too late to be included in 2024’s Pixel 9 series (as chip development is a lengthy process, usually starting years before release).

Google has instead decided to manufacture the SoC for testing purposes, as its successor, which will likely make it into the 2025 Pixel devices, will share many of its design elements. As we’ve learned, Google has designed a development board called “ChallengerDeep” to work on the chip.

There is, however, still the matter of Pixel 9. With Redondo out of the picture, Google needs another chip to become the Tensor G4. The solution to this problem is a new chip codenamed “Zuma Pro.” Note that the Tensor G3 — the SoC that’s coming to the Pixel 8 series — is known as “Zuma.”

The new chip is still semi-custom, co-designed with Samsung’s System LSI division, and will most likely be a smaller upgrade than initially planned. This is similar to how Tensor G2 (codename “Whitechapel Pro”) was a modest update over the original Tensor (“Whitechapel”). The chip currently runs under a development board codename “Ripcurrent 24” (also referred to as “Ripcurrent Pro”), whereas the Tensor G3 used just “Ripcurrent”.

Partnering with Samsung on phones makes sense. I have always wondered why Google phones have failed.
 
Partnering with Samsung on phones makes sense. I have always wondered why Google phones have failed.
Speaking for myself, I always saw Google's phones (specifically its hardware) as distinctly inferior to the competition's flagships. Yes, Google's belief that the Pixels are the "smartest" phones around due to their software might hold some water but why not pair that with cutting-edge hardware like Samsung?!

The Google Tensors (based on Samsung's Exynos chips) were always inferior (slower, hotter and less efficient) to Qualcomm's Snapdragon chips. Google's marketing specifically mentions that their Tensor chips were designed specifically for AI tasks. Well...come earlier this year, Google says its smallest new AI model (Gemini Nano) won't be coming to the Pixel 8 because of hardware limitations but it's sibling, the Pixel 8 Pro, will be able to run the Gemini Nano model. Wonderful....except Samsung S24 Ultra (using the Snapdragon 8 Gen 3) will run an even superior Google AI model, Gemini Pro! 🙄

Rumor is that the Google Pixel 9 will be feature a "minor" update to the processor. I'll wait....I do plan on buying the Google Pixel eventually...once Google switches over to using TSMC! 😁
 
Rumor is that the Google Pixel 9 will be feature a "minor" update to the processor. I'll wait....I do plan on buying the Google Pixel eventually...once Google switches over to using TSMC! 😁
That's exactly what I heard a lot: Waiting for tsmc made SOC.

Regards to hardware, one of reasons that Google not using the best inferior in the market might be due to low quantity/bargain power.
 
Intel p
I see how Apple get most of TSMC's N3. I was actually referring to whether Intel Product took up most of Intel's own capacity.
Intel products take up 99% intels capacity. This was shown in the 10Q and my report. As of Q1, There are no foundry customer taking meaningful volume from Intel (again review 10Q).

Which non-intel product in the market today is using Intel Foundry? (I need them for teardowns, but I havent found any)
 
Intel p

Intel products take up 99% intels capacity. This was shown in the 10Q and my report. As of Q1, There are no foundry customer taking meaningful volume from Intel (again review 10Q).

Which non-intel product in the market today is using Intel Foundry? (I need them for teardowns, but I havent found any)
The only thing is the Ericsson chip on Intel 4
 
Intel p

Intel products take up 99% intels capacity. This was shown in the 10Q and my report. As of Q1, There are no foundry customer taking meaningful volume from Intel (again review 10Q).
How can you in one sentence quote intel's own financial numbers, and in the next sentence say that intel cost is 200% of TSMC cost with a straight face. From intel's own numbers intel products COGS increased not decreased with the new reporting and logically speaking there is no reasonable way for your defective model to give you those numbers without making assumptions that are obviously very poor. Assuming a 15% wafer cost adder per node your model is telling you that an intel 32nm wafer should cost a similar amount to a TSMC N7 wafer, and an intel 7 wafer should cost around an A10 wafer (CFET, highNA, self aligned contacts, sub 20nm MMP, Ru or Mo metalization). There is simply no universe where either statement could be even remotely close to the truth. I also made a similar argument a while back, where TSMC's gross margins would need to be in the 70-90% range (instead of the low 50s like they are now) for your numbers to even begin to be plausible. Be it me or Scotten we both think your models are utterly preposterous.
Which non-intel product in the market today is using Intel Foundry? (I need them for teardowns, but I havent found any)
Intel has shown on multiple occasions that currently 100% of external revenue is from the OSAT business. I think they talked about broadcom as a 2D packaging customer before, and AWS has specially called out that Graviton CPUs use EMIB for 2.5D integration.
1720547860886.png

We are pleased to be one of Intel’s early customer leveraging their semiconductor packaging capabilities for our data center infrastructure. - SVP of AWS infrastructure and support

The only thing is the Ericsson chip on Intel 4
That doesn't count as an external foundry chip since it is designed by intel products. It is a custom ASIC from NEX that just so happens to use intel 4. Intel on their process roadmap even used the same terminology.
 
How can you in one sentence quote intel's own financial numbers, and in the next sentence say that intel cost is 200% of TSMC cost with a straight face. From intel's own numbers intel products COGS increased not decreased with the new reporting and logically speaking there is no reasonable way for your defective model to give you those numbers without making assumptions that are obviously very poor. Assuming a 15% wafer cost adder per node your model is telling you that an intel 32nm wafer should cost a similar amount to a TSMC N7 wafer, and an intel 7 wafer should cost around an A10 wafer (CFET, highNA, self aligned contacts, sub 20nm MMP, Ru or Mo metalization). There is simply no universe where either statement could be even remotely close to the truth. I also made a similar argument a while back, where TSMC's gross margins would need to be in the 70-90% range (instead of the low 50s like they are now) for your numbers to even begin to be plausible. Be it me or Scotten we both think your models are utterly preposterous.

Intel has shown on multiple occasions that currently 100% of external revenue is from the OSAT business. I think they talked about broadcom as a 2D packaging customer before, and AWS has specially called out that Graviton CPUs use EMIB for 2.5D integration.



That doesn't count as an external foundry chip since it is designed by intel products. It is a custom ASIC from NEX that just so happens to use intel 4. Intel on their process roadmap even used the same terminology.
I think you are getting to into the weeds for the answer. the CFO gives us the answer with numbers

Intel wafer cost is 2x that of TSMC. I said that before Intel announced their foundry numbers (which is for sales to Intel). People disagreed. Then the foundry numbers came out. showing that when they pay foundry market price, rather than cost, the foundry loses 6-8B per year. Everyone freaked out

If you look at gross margin from TSMC, is shows Intels wafer cost is 2x TSMC. the CFO does not deny this (and he given reasons how it will be fixed). I would be glad to go through the details with you and you can argue... I will set up a zoom.

oversimplified reason: Intel runs half the number of revenue wafers at each fab compared to what Scotten has modeled. This was shown at Foundry day and Intel agrees this is the problem. Production wafer cost is difference. Not theoretical cost. This is why the previous CEO wanted to save billions by outsourcing 80% of products to TSMC (TSMC price is better than Intel cost).

I will send you and scotten email to set up zoom meeting. every one is free to attend. and I will post how intel will recover from this.

I would love to get feedback. thanks!
 
Back
Top