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PCIe 7.0 is launching this year – 4x bandwidth over PCIe 5.0

XYang2023

Well-known member
PCI-SIG has just released version 0.7 of the PCIe 7.0 standard to its members, paving the way for a full launch later this year. PCI Express 7 will deliver a 4x boost over PCI Express 5, the standard used by today’s top-of-the-line PCs.

This new standard creates a pathway towards faster SSDs, stronger AI accelerators, and superior graphics cards. At CES 2025, we saw Phison push the limits of PCIe 5.0 with their “Ultimate Gen5” E28 SSD controller, clearly showing the need for faster interconnects.

The PCIe 7.0 standard is due to be released in 2025, creating an upgrade path for users of the PCI Express standard. Below are some of the improvements that PCIe 7.0 will feature.
  • Delivering 128 GT/s raw bit rate and up to 512 GB/s bi-directionally via x16 configuration
  • Utilizing PAM4 (Pulse Amplitude Modulation with 4 levels) signaling
  • Focusing on the channel parameters and reach
  • Continuing to deliver low-latency and high-reliability targets
  • Improving power efficiency
  • Maintaining backwards compatibility with all previous generations of PCIe technology

  • PCIe’s development is ahead of schedule
PCI-SIG aims to double the bandwidth of their PCIe standard every three years. With PCI Express 7, PCI-SIG will have delivered 512 GB/s of bandwidth three years ahead of schedule. This is good news for users of the PCI Express standard, as this gives them a clear upgrade path. Without this upgrade path, PCI-SIG members would need to consider alternative standards whenever they need more bandwidth. By continuously improving PCIe, PCI-SIG can maintain PCI Express as the gold standard of PC connectivity.



I was wondering when I could replace my dual RTX 3090 (NVLink) with something else.




If Intel releases a GPU in the future that supports PCIe 7.0 and comes with 24GB, 32GB, or even 48GB of memory, a dual-GPU setup could work really well, I think.
 
Last edited by a moderator:
IIRC PCIe 5.0 was (relative to 4.0) expensive to implement because it achieved performance gains mainly via frequency, but 6.0 is a 'relatively easy' upgrade as it doesn't require signalling / wiring changes (an encoding change to PAM4).

I see PCIe 7.0 is still using PAM4. Does PCIe 7.0 another frequency increase (with drawbacks on heat, power, etc) or are they doing something else to increase performance? i.e. is it going to be easy or hard relative to PCIe 6.0?
 
IIRC PCIe 5.0 was (relative to 4.0) expensive to implement because it achieved performance gains mainly via frequency, but 6.0 is a 'relatively easy' upgrade as it doesn't require signalling / wiring changes (an encoding change to PAM4).

I see PCIe 7.0 is still using PAM4. Does PCIe 7.0 another frequency increase (with drawbacks on heat, power, etc) or are they doing something else to increase performance? i.e. is it going to be easy or hard relative to PCIe 6.0?
I am not sure. I simply look at the data transfer rate.
 
IIRC PCIe 5.0 was (relative to 4.0) expensive to implement because it achieved performance gains mainly via frequency, but 6.0 is a 'relatively easy' upgrade as it doesn't require signalling / wiring changes (an encoding change to PAM4).

I see PCIe 7.0 is still using PAM4. Does PCIe 7.0 another frequency increase (with drawbacks on heat, power, etc) or are they doing something else to increase performance? i.e. is it going to be easy or hard relative to PCIe 6.0?
Ar... FLIT mode in PCIe 6.0 is like a brand new design.
 
Ar... FLIT mode in PCIe 6.0 is like a brand new design.
Thanks - understand it's brand new design but that means a PCB "wired" for 5.0 should work with 6.0 if the logic chips on both sides of the wiring support 6.0, right?
 
doesn't require signalling / wiring changes (an encoding change to PAM4).

No, PAM4 is a massive PITA. PAM4 PHYs are massive power hogs, with too much of analog trickery happening behind the veil of the hard macro IP block. Reminding me of 10GbE over copper: actual decoding 1/10 of the die, analog magic, and DSP trickery to make that happen 7/10 of the die.

I see PCIe 7.0 is still using PAM4. Does PCIe 7.0 another frequency increase (with drawbacks on heat, power, etc) or are they doing something else to increase performance? i.e. is it going to be easy or hard relative to PCIe 6.0?

My prediction: PCIE 4 would be the last mobile PCIE version until they make a dramatic leap in power efficiency at higher frequencies.
 
No, PAM4 is a massive PITA. PAM4 PHYs are massive power hogs, with too much of analog trickery happening behind the veil of the hard macro IP block. Reminding me of 10GbE over copper: actual decoding 1/10 of the die, analog magic, and DSP trickery to make that happen 7/10 of the die.



My prediction: PCIE 4 would be the last mobile PCIE version until they make a dramatic leap in power efficiency at higher frequencies.
We already got PCI-E 5 on mobile tbf
 
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