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Over 100 million wafers shipped with EUV multipatterning, >95% claimed by Lam Research

Fred Chen

Moderator
Lam Research claims over 95% of the more than 100 million wafers processed with multipatterning (193i and EUV), particularly highlighting 5nm logic node.


LRC EUV Multipatterning over 100 Million Wafers.png
 
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Fred Chen

Moderator
Will high-NA EUV go back to single expo?
The maximum exposure field size on high NA is 26 mm x 16.5 mm, whereas on all the current platforms it's 26 mm x 33 mm. Most masks make use of most of the 26 mm x 33 mm area, so the high-NA needs to expose in two steps, with alignment (stitching) between the two exposures, like a double exposure. So there is definitely field splitting causing double exposure, but whether there is also pitch splitting depends mainly on whether 15 nm or less can be achieved practically in resist (accounting for electron spread), as well as stochastic control. For example, even with electron-beam lithography, 15 nm already needs double patterning (e.g., https://www.spiedigitallibrary.org/...nt-lithography/10.1117/12.2567043.short?SSO=1, https://www.nature.com/articles/nature03719).

Another detail to consider for high-NA is polarization. Studies just starting it seems, but it looks like it's another source of image "fading".
 
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Paul2

Active member
22*16 will fit expensive smartphone SoCs. They just need to remove NPUs, and other waste of silicon. Possibly go for stacked L3. I think you can even fit 2 top tier SoCs into 22*16 with its transistor density.
 

Fred Chen

Moderator
22*16 will fit expensive smartphone SoCs. They just need to remove NPUs, and other waste of silicon. Possibly go for stacked L3. I think you can even fit 2 top tier SoCs into 22*16 with its transistor density.
SoC dies generally fit into much less than 26 mm x 16.5 mm, but multiple dies are stuffed into the 26 mm x 33 mm to maximize productivity on the current tools. For example 2 x 3 dies, for a 9 mm x 11 mm Bionic SoC.

This would require stitching in order for 26 x 16.5 mm to accommodate. Otherwise, if field size just shrank to 26 mm x 16.5 mm globally, the entire line productivity (over all the layers) would go down.
 
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Paul2

Active member
SoC dies generally fit into much less than 26 mm x 16.5 mm, but multiple dies are stuffed into the 26 mm x 33 mm to maximize productivity on the current tools. For example 2 x 3 dies, for a 9 mm x 11 mm Bionic SoC.

This would require stitching in order for 26 x 16.5 mm to accommodate. Otherwise, if field size just shrank to 26 mm x 16.5 mm globally, the entire line productivity (over all the layers) would go down.
Aren't DUV tools many, many times faster than EUV now, and stitching be the main bottleneck, not DUV stepper performance?
 

Fred Chen

Moderator
Another detail to consider for high-NA is polarization. Studies just starting it seems, but it looks like it's another source of image "fading".

It seems polarization is something they possibly want to control for high NA EUV: https://www.spiedigitallibrary.org/...zation-effects/10.1117/12.2599904.short?SSO=1

The normalized image log-slope (NILS), the key image quality metric, was found to fall below 2 for 16 nm half-pitch, when using unpolarized, but improved above 2 by using the suitable polarization (parallel to the lines). So there is a thought to use multilayers specifically for polarization. It also entails maybe two exposures, one for horizontal lines, one for vertical lines.

An earlier study by EIDEC confirmed the partial polarization effect: https://www.spiedigitallibrary.org/...Field-Exposure/10.1117/12.2219368.short?SSO=1

It can also be accessed here: http://euvlsymposium.lbl.gov/pdf/2016/Poster/P-EE-06.pdf

The partial polarizing effect is shown in the excerpt below.

Successive mirrors as s-polarizer.png
 
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Paul2

Active member
It seems polarization is something they possibly want to control for high NA EUV: https://www.spiedigitallibrary.org/...zation-effects/10.1117/12.2599904.short?SSO=1

The normalized image log-slope (NILS), the key image quality metric, was found to fall below 2 for 16 nm half-pitch, when using unpolarized, but improved above 2 by using the suitable polarization (parallel to the lines). So there is a thought to use multilayers specifically for polarization. It also entails maybe two exposures, one for horizontal lines, one for vertical lines.

An earlier study by EIDEC confirmed the partial polarization effect: https://www.spiedigitallibrary.org/...Field-Exposure/10.1117/12.2219368.short?SSO=1

It can also be accessed here: http://euvlsymposium.lbl.gov/pdf/2016/Poster/P-EE-06.pdf

The partial polarizing effect is shown in the excerpt below.

View attachment 599

How much transistor density/performance trade-off goes for double pattern EUV? My impression always was that EUV is there to avoid catastrophic productivity decline as multiple-patterning gets more extensive (quad, and octuple,) and otherwise EUV is not a trade-off worth taking.

I will be very surprised to see the industry doing a U-turn on it, after being bullish on "EUV single exposure, or bust"
 

Fred Chen

Moderator
How much transistor density/performance trade-off goes for double pattern EUV? My impression always was that EUV is there to avoid catastrophic productivity decline as multiple-patterning gets more extensive (quad, and octuple,) and otherwise EUV is not a trade-off worth taking.

I will be very surprised to see the industry doing a U-turn on it, after being bullish on "EUV single exposure, or bust"
My understanding was that 5/4nm already had some EUV multipatterning and 3nm even more. For something like SALELE for the metal layers, it would be 4 masks. The center-to-center for contacts could be less than 30 nm, requiring triple patterning. Perhaps for TSMC, the multipatterning barrier is less of an issue, since they've done it for a long time already.
 
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