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OpenHW Group to showcase member projects based on CV32E and CV64A open source cores at the RISC-V Summit 2020

Daniel Nenni

Staff member
OpenHW Group to showcase member projects based on CV32E and CV64A open source cores at the RISC-V Summit 2020

Ottawa, Canada - December 9 2019: The OpenHW Group will be participating at the 2nd annual RISC-V Summit in San Jose, 10-12 December 2020. Visitors to the OpenHW Group stand - #311 – will be able to view member company demonstrations of the CORE-V family of cores and see the rapid evolution of the organisation since its launch in June this year. Companies showcasing at the OpenHW Group booth are Bluespec, CMC Microsystems, Embecosm, Greenwaves Technologies, Metrics, NXP and Onespin Solutions.

President and CEO, Rick O’Connor will present a keynote speech on the 2nd day of the event and other members of the OpenHW Group team will participate in panel discussions. In the past six months since the organisation was started with thirteen supporting members, the non-profit organisation has seen its membership agreement and bylaws ratified by the Board of Directors and has grown to nineteen members, with many more in the process of signing up.

“Our participation at the RISC-V Summit marks a milestone in the starting journey of the OpenHW Group and demonstrates the power of a collaborative approach, with so many projects in progress,” said Rob Oshana, Chairman of the Board, OpenHW Group and VP Software Engineering, NXP. “We have made very good progress in a short space of time and the Summit provides the perfect platform to showcase open source processor development in the context of a deep ecosystem that supports the adoption of the RISC-V ISA.”

“We are extremely pleased at how far we’ve come since our launch in June,” said Rick O’Connor, President and CEO, OpenHW Group. “In fact, at the Summit, we will be announcing a particularly aggressive goal for 2020 that will form the basis of more multi-core devices, and will truly put open source hardware, IP and tools on the map.”

OpenHW Group will be participating in the RISC-V Summit conference agenda as follows:

• Wednesday December 11 @10:05am Grand Ballroom 220-A – “Open source processor IP for high volume production SoCs: CORE-V family of RISC-V cores.” - Rick O’Connor, President and CEO OpenHW Group
• Wednesday December 11 @2:20pm Grand Ballroom 220-A – “Processor IP showcase with Andes Technology, CHIPS Alliance, Codasip, Shakti Project, SiFIve, Syntacore, OpenHW Group.” – Rick O’Connor, President and CEO OpenHW Group
• Tuesday December 10 @2:20pm Grand Ballroom 220-A – “The RISC-V open ISA’s shock wave of processor innovation that’s causing a seismic shift in SoC verification requirements.” – Panel discussion with Mike Thompson, Director of Engineering, Verification Task Group OpenHW Group

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For further information and reader enquiries:
Rick O’Connor, President & CEO
Phone: +1 (613) 614-4101 Email:

Agency contact:
Andrea Barnard, Publitek Limited
Phone: +44 7768 178356 Email:

About the OpenHW Group
OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software such as the CORE-V Family of cores. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices.

CORE-V is a series of RISC-V based open-source cores with associated processor subsystem IP, tools and software for electronic system designers. The CORE-V family provides quality core IP in line with industry best practices. The IP is available in both silicon and FPGA optimized implementations. These cores can be used to facilitate rapid design innovation and ensure effective manufacturability of high-volume production SoCs.

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