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There will be a discussion at a BoF meeting on extending the IR (intermediate representation) to support parallel constructs at the LLVM developers conference in November. Currently LLVM and Gcc don't support the light-weight reactive threading model used by HDLs, so this is a chance to suggest adding it.
HDL/CSP extensions would also support neural network programming and heterogeneous messaging passing which are useful in the IoT/big-data space, so there is a reasonable chance of getting support for the effort.
An LLVM infrastructure supporting the right threading models will make it easy to build an open-source SysytemVerilog/VHDL with the full debug and profiling capabilities missing in the commercial tools, and truly portable.
I develop the CVC Verilog compiler. What light weight threading model? Verilog
and I think VHDL work beause of the stratified event queue model with 6 or so
levels in each clock cycle initial and pound 0 loop. Average number of evaluation
machine instructions before scheduler interaction in Verilog is something like 5.
Simulation uses 1364 Verilog semantics. SV is for test bench developers.
I develop the CVC Verilog compiler. What light weight threading model? Verilog
and I think VHDL work because of the stratified event queue model with 6 or so
levels in each clock cycle initial and pound 0 loop. Average number of evaluation
machine instructions before scheduler interaction in Verilog is something like 5.
Simulation uses 1364 Verilog semantics. SV is for test bench developers.
What's missing in C/C++ is that there's no easy way to react to events. That's an upshot of the only active things in C being routines, and starting a thread requires calling a routine (on a new stack). If you use C++ you can base a thread on a thread-class object that can exist without a stack.
So to create a Verilog/VHDL-like process in C++ requires being able to define a class-like object which contains a piece of code (which may be a loop) with suspension and resumption methods such that suspension doesn't require a persistent stack. Then you just need a couple of first-class language template-like objects for signals and pipes (examples here - http://parallel.cc).
The scheduling model isn't that important, for a software-defined hardware (SDx) flow you want something asynchronous that supports message passing. You can layer something fancy over the basic support mechanisms if you feel the need to replicate Verilog/VHDL RTL behavior.
