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? on Packaging, Layers Replacing Node Shrink

Arthur Hanson

Well-known member
With nodes of 5nm and below getting increasingly expensive and difficult to produce, will additional sophisticated layering and packaging technologies become the next area of significant advancement in the semi sector? Also will this be how shrink using layers and packaging will be applied to MEMS and increase the opportunities for their usefulness? Memory has been using ever increasing layers and could sophisticated packaging extend the shrink being applied? Any thoughts on other paths the semi/nanotech sector will be using for increased performance at lower cost would be appreciated.
 

clhende

New member
I think that packaging can be used to help reduce the size of the electronic system somewhat further. The combination of Through-Silicon Vias (TSVs), Direct Chip Attach, and silicon thinning can facilitate stacking of chips to create smaller form factors in system applications. I do believe that the path of least resistance now is no longer smaller, but up (in the third dimension). A lot of work remains to be done, but heterogenous silicon integration should be a big driver in systems going forward.

Another possibility is Monolithic 3D integration (touted by SOITEC and a few others), but I don't see that gaining traction until well into the future, if ever.
 

Arthur Hanson

Well-known member
I think that packaging can be used to help reduce the size of the electronic system somewhat further. The combination of Through-Silicon Vias (TSVs), Direct Chip Attach, and silicon thinning can facilitate stacking of chips to create smaller form factors in system applications. I do believe that the path of least resistance now is no longer smaller, but up (in the third dimension). A lot of work remains to be done, but heterogenous silicon integration should be a big driver in systems going forward.

Another possibility is Monolithic 3D integration (touted by SOITEC and a few others), but I don't see that gaining traction until well into the future, if ever.
clhende, Do you ever think the industry will be able to stack chip many chip functions like they stack memory where they can stack up to 96 layers? Do you see any entirely new stacking technologies on the horizon?
 

Jim H

New member
For now, one of the best looking options IMO is the Silicon interconnect fabric (Si-IF) being developed within the CHIPS consortium at UCLA. The idea allows one to design a pseudo-SoC using chiplets of any sort, and it imagines getting rid of SerDes, and getting rid of the PCB completely. While Si-IF is a 2D solution, one could certainly put stacked chips on this mesh, just like we put HBM next to FPGA's or GPU's today using interposers or Intel EMIB's. Si-IF is kind of the ultimate evolution of EMIB.
 

Arthur Hanson

Well-known member
For now, one of the best looking options IMO is the Silicon interconnect fabric (Si-IF) being developed within the CHIPS consortium at UCLA. The idea allows one to design a pseudo-SoC using chiplets of any sort, and it imagines getting rid of SerDes, and getting rid of the PCB completely. While Si-IF is a 2D solution, one could certainly put stacked chips on this mesh, just like we put HBM next to FPGA's or GPU's today using interposers or Intel EMIB's. Si-IF is kind of the ultimate evolution of EMIB.
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