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NVIDIA Once Again Teases Potential Deal With Intel: Says Would Love To Have A Third Foundry Partner Besides TSMC & Samsung

You can get there first order quickly (slow down the clocks, etc). Make it functional. You know that they are going to want to jam more stuff in. My point is that there isn't a reason to wait. They can migrating over and prove out what they have without taping out. That is what simulators are for. The US is the safest place to fab a chip right now. In parallel, I assume Intel is willing to provide the first pass conservative rules in 18A with the rev0 models. This also allows the PDK to get flushed out, standard cells, I/O, etc to be created.
Lets not make this too complex.
1) Intel is new to foundry. They currently are about 1/30th the size of TSMC in terms of revenue. Intel obviously can make chips and technologies
2) No large company is going to bank on Intel with majority of its volume for several years. They will be tested, then partial volume/backup, then a decision will be made to ramp or not. There will be tons of PR in the mean time.
3) Intel has plans for new technologies, but Intel has a long history of not delivering on time and being very expensive. they need to fix those
4) 18A is the finish line per Pat. According to intel, they need to run multiple Intel internal products before ramping foundry. This is a 2026 foundry ramp at the earliest.
5) Reminder: Intel chooses to run multiple chiplets and entire chips on TSMC.... now and in the future. There might be a reason for that

So aside from details on patterning, DRC, PDK..... Intel has to prove itself before large companies ramp.

Our model shows intel external revenue by year.... it is probably optimistic.... it is less than half of what some people have claimed for Intel Foundry revenue.
When Intel tried to be a foundry last time they were not using industry standard EDA, which I heard caused problems when dealing with outside customers. It seems like those days are gone and Intel can certainly take advanced designs to TSMC using tools others use, so they probably have solved that problem. Which is not to say Blue's other concerns are not valid, just that some of them are past.

@Tanj , more like using standard EDA tools in non-standard ways via some proprietary utilities and methodologies grafted on, in a Frankenstein flow kind of approach. Add on that characterization of internal IP, including std. cells, was done for a proprietary (processor) design style, that really couldn't be duplicated by end-users. That Intel designers could use standard design tools in a standard design flow based on standard characterization to fab Intel chips via TSMC, was a total wake-up call for the DT team.