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It seems to me that the lithography industry doesn't ever sit still. They're always trying to move to the next node, improve yields, etc.. So it is with no small curiosity that though I have been looking, I have not heard of anything beyond high-NA EVU. TSMC, Samsung, and Intel project extended lead times for the next few nodes, making me wonder how slowly lithographic tech is going to advance and if they're working on anything more or just saying, "It's gotten too hard and expensive now. Let's stop."
My own searches online have turned up some interesting information, like this, What's Next for EUV? , but that only discusses things like improving masks, not how to get smaller and smaller feature sizes with the same or a different wavelength.
So what is next? Is ASML's High-NA TwinScan machine the last step, or is there something else on the horizon?
Thanks!
PS: I'm not asking about the possibility of using different materials, although that's always interesting.
This is close minded. Materials and architecture have been the main drivers of transistor scaling over the past two decades.
But to answer your question ASML is doing pathfinding work to consider the plausibility of 0.7 NA EUV. Newer photoresits, pelicals, stochastic defect reduction tools, and stronger power supplies will allow for EUV tools to yield at lower doses or slightly push higher resolutions without trashing throughputs.
Besides the tools themselves you will see/are seeing an increase in the adoption of self aligned processes to allow for higher densities at the same resolutions. On N3 we are finally seeing TSMC develop a self aligned contact scheme. TSMC also released papers talking about the possibility of having self aligned vias for post N3 nodes. Directed self-assembly offers the potential to be the penultimate of self aligned patterning techniques. It can serve as a massive resolution booster for more typical lithographic techniques. More traditional self aligned patterning schemes also allow for higher resolutions over what would otherwise be possible with direct print or multipass LE schemes. Heck for DUV SAQP you can reach high-na resolutions. More realistically EUV SALELE and or SADP could carry low and high-NA EUV a good ways further.
The trend in lithography has always been to increase the photon energy. 193 nm was the last non-ionizing wavelength, ~6.4 eV. Since EUV is ionizing, the wafer in an EUV system is already immersed in a hydrogen plasma, as is the mask, and all the optical elements.
... Heck for DUV SAQP you can reach high-na resolutions. More realistically EUV SALELE and or SADP could carry low and high-NA EUV a good ways further.
The TL;DR on that is that each feature on the target is formed by the interference pattern from a patch on the source mask which is larger than just the feature - due to wave nature of light. If you try to print every feature using just one exposure then the neighboring features compete and overlap their source patches on the mask, resulting in compromises which require sizes and spacings to be dialed back.
But if you can split your pattern into 2 or even 3 masks then you can separate out most of the adjacencies and give each feature 2 or 3 times as much area on the source mask for inverse lithography (ILT) to work its magic to improve shapes and keep things in the proper place.
That interview seems already dated. ASML have been presenting 0.70 with more confidence recently. Still not a sure thing, but they have done some good work including a design to reduce the mirror count.
That interview seems already dated. ASML have been presenting 0.70 with more confidence recently. Still not a sure thing, but they have done some good work including a design to reduce the mirror count.
It's about a half year ago; his concerns were primarily economic or financial. Still, going to 0.7NA necessarily requires polarization consideration, which would be an added complexity if not gotcha for EUV.
It's about a half year ago; his concerns were primarily economic or financial. Still, going to 0.7NA necessarily requires polarization consideration, which would be an added complexity if not gotcha for EUV.
If they showed the arrangement, we might be able to judge. On the other hand, if it was not mentioned, it probably was left out or not even considered.
If they showed the arrangement, we might be able to judge. On the other hand, if it was not mentioned, it probably was left out or not even considered.
But to answer your question ASML is doing pathfinding work to consider the plausibility of 0.7 NA EUV. Newer photoresits, pelicals, stochastic defect reduction tools, and stronger power supplies will allow for EUV tools to yield at lower doses or slightly push higher resolutions without trashing throughputs.
Even if NA will go up, and allow less n-patterning, the physical limit on how small you can make a GAA transistor is very close, and even moving away from silicon will not provide much of extra runway. The next scaling driver after 5-6 years will definitely be going 3D. There is simply no other option physically.
Even if NA will go up, and allow less n-patterning, the physical limit on how small you can make a GAA transistor is very close, and even moving away from silicon will not provide much of extra runway... There is simply no other option physically.
Not so. From TSMC 28nm to N5 transistor density increased by about 9.5x. This is post the death of Dennard scaling and post the easy litho era. During this period cpp went from 117nm to 51nm (only a 0.44x reduction). GAA can offer much tighter gate pitches, and new materials can further tighten this up. While I don't think the current SiGe PMOS used on N5/N3 would work on N2, but when high mobility PMOS and NMOS channels become a thing for GAA nodes they too will offer significant scaling opportunities. Given how little CPP scaled over the past decade compared to overall transistor density, wouldn't count out the idea of continued device scaling over the next 10 years.
Of course 3D will play a major role going forward, and the path to additional device scaling will be very hard. However people saying "device scaling is done" sound a whole lot like the folks saying "the transistor can scale no further" right before strain, HKMG, finFET, and self aligned processes came into the limelight and proved those doubts wrong time after time.
Of course 3D will play a major role going forward, and the path to additional device scaling will be very hard. However people saying "device scaling is done" sound a whole lot like the folks saying "the transistor can scale no further" right before strain, HKMG, finFET, and self aligned processes came into the limelight and proved those doubts wrong time after time.
Prior we dealt with physical limits of fabrication, now we deal with physical limit of the device itself.
The theoretical minimal sizes of GAA transistors are well known. Density boosters looking forward are more design, and materials related than trying to make gate and channel physically smaller.
What I mean is that even if you will use eBeam tool to fabricate the smallest transistor design known to work, you will not be far to what the industry expects in 5-7 years at current scaling rate.
In the late 90s the issue was not manufacturing it was the devices themselves. If intel wanted to make a 90 or 45nm device without strain, those devices would have used as much energy in the off state as when they were on. While the rest of the industry was languishing and couldn't scale devices any further due to gate thickness reaching the single crystal lattice levels HKMG saved the day and allowed planar devices (and later 3D devices) to continue scaling to smaller dimensions. Without finFET you have nodes with underwhelming performance characteristics like 20nm.
The limit of planar CMOS devices were well know in 1990s. That didn't stop planar devices from scaling FAR further than they should have been able to due to said material innovations (no DTCO tricks even required).
We have already been seeing this for the past decade. Furthermore ALL lithographic shrinks since the late 90s have been off the back of better materials. All the way from Cu interconnects to high mobility channel materials. But like I said I agree that further DTCO optimizations, backside power delivery networks, and later CFETs will be key enablers of further scaling. However I would not discount the enabling work that new materials can and will offer to further shrink devices past what is conventionally possible with current epitaxial growth techniques, current metal gate tech, Si channel HNS devices, and modern Cu metalization schemes.
Given how little CPP scaled over the past decade compared to overall transistor density, wouldn't count out the idea of continued device scaling over the next 10 years.
I'm relying on google translate for reading this article so don't crucify me if I didn't understand the article correctly:
The 48nm CPP was referring to 3GAE and a 22nm min metal pitch. For one 3GAE is probably significantly behind N3E in density. Therefore this CPP being worse than N3 (45nm) does not indicate GAA is bad. Two TSMC using GAA for N3 also does not indicate that GAA is bad either, just that it isn't ready yet, and that TSMC saw there was barely enough gas left in the finFET tank to go one more gen on a proven technology. Three N3 had a CPP of 45nm (granted N3E is probably reducing this). If a finFET node could do 45nm I don't see why GAA couldn't scale past this given the superior channel control. As nanosheet stack count grows you can also have narrower nanosheets, and the narrower the nanosheets have better the channel control. Four this projections also don't seem reasonable. A 22nm min metal pitch seems unhelpful given the small density shrink 3GAE brings, and unlikely given that N3 doesn't even go that small. Lastly there is no indication that early HNS designs have to be similar or worse PPW than finFETs. intel 4 seems to be around N3E in this respect, intel 3 will supposedly go to around N2 or N3P/X PPW, and yet intel is guiding that intel 20/18A are expected to be full node levels of improvement over intel 3 on the PPW front.
I think the numbers I have seen Scotten throw around were 45nm cpp for silicon channel HNS devices. Given how analysts and IMEC folks don't have access to the most juicy stuff it is also always possible to get unexpected breakthroughs thrown at us that challenge what we thought was possible. The most recent example would probably be intel 4 having a 5.33 track HP cell. A 5 track cell was theoretically possible, but nobody was doing that on even their high density devices. Now newer imec papers are theorizing about the possibility of 4 track finFET cells without BSPDNs. Obviously this is a DTCO example rather than a CPP or device scaling example that shocked everybody, but you get my point. Nobody knows when the next SiGE PMOS fin or finFET moment will come. These sorts of things tend to get played close to the chest for maximum effect.
