G
glforte
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There a growing number of reports in the trade press highlighting the need for a new class of verification checks aimed at chip reliability. To catch subtle design errors that can lead to early failures in the field, you need to be able to identify classes of circuits, (thin oxide PMOS, for example), appropriately identify the voltages for the pins on that device (including any bulk biasing), and compare them against the specific rules for that device and voltage domain. We have been working with customers on multi-power domain ERC requirements such as these using circuit and layout information to develop more sophisticated reliability checks.
I’d like to expand the discussion on this important class of verification challenges. If you are finding it difficult to perform specific circuit or physical verification checks, let’s discuss them in this forum and see what kind of solutions might be available based on other readers’ experiences. I’ve posted an article about this topic on this site at: http://www.semiwiki.com/forum/content/360-new-erc-tools-catch-design-errors-lead-circuit-degradation-failures.html . Also visit Matt Hogan's blog at http://blogs.mentor.com/matthew_hogan/.
Mentor will be presenting on this topic at the free Tech Design Forum on March 10 in Santa Clara (http://www.edatechforum.com/events/santa-clara/event.cfm). Look for the session “Successful Analog Mixed Signal Design at Advanced Nodes.”
There is also more information about Calibre PERC, an ERC tool that addresses this type of design error, at http://www.mentor.com/products/ic_nanometer_design/techpubs/addressing-reliability-and-circuit-verification-challenges-with-calibre-perc-42217 and http://www.mentor.com/products/ic_nanometer_design/multimedia/circuit-verification-design-reliability .
I’d like to expand the discussion on this important class of verification challenges. If you are finding it difficult to perform specific circuit or physical verification checks, let’s discuss them in this forum and see what kind of solutions might be available based on other readers’ experiences. I’ve posted an article about this topic on this site at: http://www.semiwiki.com/forum/content/360-new-erc-tools-catch-design-errors-lead-circuit-degradation-failures.html . Also visit Matt Hogan's blog at http://blogs.mentor.com/matthew_hogan/.
Mentor will be presenting on this topic at the free Tech Design Forum on March 10 in Santa Clara (http://www.edatechforum.com/events/santa-clara/event.cfm). Look for the session “Successful Analog Mixed Signal Design at Advanced Nodes.”
There is also more information about Calibre PERC, an ERC tool that addresses this type of design error, at http://www.mentor.com/products/ic_nanometer_design/techpubs/addressing-reliability-and-circuit-verification-challenges-with-calibre-perc-42217 and http://www.mentor.com/products/ic_nanometer_design/multimedia/circuit-verification-design-reliability .
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