[content] => 
    [params] => Array
            [0] => /forum/index.php?threads/new-erc-tools-needed-to-catch-design-errors-that-lead-to-circuit-degradation-failures.459/

    [addOns] => Array
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2020771
            [XFI] => 1050170

    [wordpress] => /var/www/html

New ERC Tools Needed to Catch Design Errors that Lead to Circuit Degradation Failures


New member
There a growing number of reports in the trade press highlighting the need for a new class of verification checks aimed at chip reliability. To catch subtle design errors that can lead to early failures in the field, you need to be able to identify classes of circuits, (thin oxide PMOS, for example), appropriately identify the voltages for the pins on that device (including any bulk biasing), and compare them against the specific rules for that device and voltage domain. We have been working with customers on multi-power domain ERC requirements such as these using circuit and layout information to develop more sophisticated reliability checks.

I’d like to expand the discussion on this important class of verification challenges. If you are finding it difficult to perform specific circuit or physical verification checks, let’s discuss them in this forum and see what kind of solutions might be available based on other readers’ experiences. I’ve posted an article about this topic on this site at: . Also visit Matt Hogan's blog at

Mentor will be presenting on this topic at the free Tech Design Forum on March 10 in Santa Clara ( Look for the session “Successful Analog Mixed Signal Design at Advanced Nodes.”

There is also more information about Calibre PERC, an ERC tool that addresses this type of design error, at and .
Last edited:


A lot of this stuff can be tackled by using smarter cell/block level models in your verification flow. Verilog-AMS was originally designed to allow mixing of digital models with analog wiring models, but you can also do hybrid models that check other things like electro-migration, power consumption and thermal modeling. Pushing these checks to the back end of the process is very inefficient, and if you do you probably want to specify the rules at the design library level and above. Verilog-AMS supports plug-and-play so that you can swap views in your verification simulations without having to rewrite your test-benches.

How to make it work properly -

PS: I have some pat-pending technology in this area for handling high-variance Silicon, if anyone wants to help commercialize it.