Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/mz-technologies-updates-technology-roadmap.21516/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021370
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

MZ Technologies Updates Technology Roadmap

AmandaK

Administrator
Staff member
Rome – November 19, 2024

Tackling the barriers to 3D-IC design architecture

MZ Technologies has unveiled an updated technology roadmap for its GENIOTM branded integrated chiplet/packaging Co-Design EDA tool.
The roadmap calls for major improvements throughout 2025, starting with four major additions to a new GENIO’s product that will be unveiled in the mid-January timeframe. Other new features will be added around mid-year and at year’s end.

The new features to be announced at the first of the year address some of most vexing advanced systems challenges. The latest vision calls for tackling thermal and mechanical issues. and will be accompanied by an improved and modernized user interface. Mid-year, MZ is expected to add additional thermal and interconnect features.

Thermal and Mechanical Stress Barriers

The new thermal and mechanical features respond to thorny considerations in next-generation 3D-ICs. In 3D-packed heterogeneous semiconductor devices, thermal stress arises from uneven heat distribution during operation, potentially leading to warping and reliability failures. Effective thermal management strategies are essential to minimize temperature differentials, ensuring optimal performance and longevity of the integrated chiplets within the package.

Mechanical stress in 3D-packed designs can result from factors such as thermal expansion mismatch and substrate flexing. These stresses can cause interconnect failures or delamination. A robust design framework must address these challenges to maintain structural integrity and performance across varying operational conditions and material interfaces.

First Available Integrated Co-Design Tool

GENIO’s proprietary, fully integrated EDA co-design tool features an end-to-end IC and packaging platform for 2D/2.5D/3D system design. It integrates existing silicon and package EDA flows to create full co-design and optimization of complex multi-chip designs that comprise advanced heterogeneous microelectronic systems.

“MZ Technologies rolled out the first commercially available co-design tool three years ago and we feel an obligation to the EDA community to continue to innovate.,” said Anna Fontanelli, Founder and CEO of MZ Technologies.

GENIO’s cross-hierarchical, 3D-aware, design methodologies streamline the entire IC eco-system. It integrates IC and advanced packaging design to ensure full system level optimization, shorten the design cycle, drive faster time-to-manufacturing and improve yields.

Media contact

Michele Taliercio
info@monozukuri.eu
+390686298287

For further information, please link to the source press release
 
Back
Top