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Mono-3D DRAM claim

Their diagram seems wrong
1683184992_66_3D-X-DRAM-multi-layer-RAM-introduced-that-could-revolutionize-the-market.png
 
Care to enlighten the more logic minded folks among us Fred? It looks like a NAND cell, but I don’t have the know how to tell you if that layout would make it totally unsuitable for DRAM. All I could tell you is that if it is using a floating gate that means the individual device needs to be much larger than the most advanced DRAM cells are today.
 
Care to enlighten the more logic minded folks among us Fred? It looks like a NAND cell, but I don’t have the know how to tell you if that layout would make it totally unsuitable for DRAM. All I could tell you is that if it is using a floating gate that means the individual device needs to be much larger than the most advanced DRAM cells are today.
The bit line (which conducts current) is adjacent the word line (which functions as a gate) separated by very thin insulation. Source line is likewise separated from the word line by thin insulation. These appear to be parasitic capacitances and leakage sources.

As I understood the announcement, the patent application was recently submitted, so won't be open to the public for some time.
 
The bit line (which conducts current) is adjacent the word line (which functions as a gate) separated by very thin insulation. Source line is likewise separated from the word line by thin insulation. These appear to be parasitic capacitances and leakage sources.

As I understood the announcement, the patent application was recently submitted, so won't be open to the public for some time.
And that sounds like countless Samsung mono3d DRAM patents
 
A rather off topic question, but could this NAND style vertical manufacturing ever potentially be feasible for logic?
Probably not. Power consumption and clock speeds of such a large device would be undesirable. You would also have a really hard time wiring it together to create the complex layouts needed for logic. Memory is much easier because it is just an array.
 
A rather off topic question, but could this NAND style vertical manufacturing ever potentially be feasible for logic?

Not with current FETs. A radically new device is needed. I wrote few month ago of VFET being so far the only option for an easy way to at least make a 6T SRAM cell with a footprint of 2T.

As said above already, isolation, and depositing metal in between layers are big challenges, with no solidly proven solution.

A billion dollar question: how to deposit new epi layers on top of amorphous/poly materials? One suggestion is just to go for monocrystalline metal.
 
The bit line (which conducts current) is adjacent the word line (which functions as a gate) separated by very thin insulation. Source line is likewise separated from the word line by thin insulation. These appear to be parasitic capacitances and leakage sources.
I don't believe that is insulator surrounding the bit line. I believe the channel with the FBE has source and drain adjacent, so that layer is source or drain. Current flows through it to and from the bit line, which might be a metal. The idea seems to be that the charge is trapped in the channel as FBE, rather than as conventional capacitors, and the cell is sensed by reading out the presence or absence of that trapped charge.

The simplicity is alluring. The charge may be quite small but the vertical data line is probably short and high quality helping it to be sensed. This was tried with planar DRAM a decade ago and never made it to market, with temperature range being one problem. But even if it is still a problem there may be markets where it could be used. But do they have working devices? Their site requires an NDA to get beyond what is in the press release.
 
A rather off topic question, but could this NAND style vertical manufacturing ever potentially be feasible for logic?
Not with the drill and plug approach which is the key to the cost savings of NAND, but also results in perfectly repeated layers with no internal variation. You might be able to have multiple layers of logic but every layer will need distinct wiring, probably 3 or four metals. And then the power density will be a challenge. So, there is some conceptual work but the closest anyone gets is with face-bonded pairs of chips for the goal of overall shorter wiring and better performance. Nothing looking like NAND.
 
I don't believe that is insulator surrounding the bit line. I believe the channel with the FBE has source and drain adjacent, so that layer is source or drain. Current flows through it to and from the bit line, which might be a metal. The idea seems to be that the charge is trapped in the channel as FBE, rather than as conventional capacitors, and the cell is sensed by reading out the presence or absence of that trapped charge.

The simplicity is alluring. The charge may be quite small but the vertical data line is probably short and high quality helping it to be sensed. This was tried with planar DRAM a decade ago and never made it to market, with temperature range being one problem. But even if it is still a problem there may be markets where it could be used. But do they have working devices? Their site requires an NDA to get beyond what is in the press release.
The main issue with the diagram is leaking between the bit line and word line through the vertical white strip, and between the word line and source, through a horizontal portion.
 
The main issue with the diagram is leaking between the bit line and word line through the vertical white strip, and between the word line and source, through a horizontal portion.
If you used a thicker high-K dialectic barrier would that give acceptable leakage between the floating gate and the bitline at the presumably large feature sizes for this device?

edit: nm I misread word line as gate somehow. However I suppose the basic idea still stands.
 
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If you used a thicker high-K dialectic barrier would that give acceptable leakage between the floating gate and the bitline at the presumably large feature sizes for this device?

edit: nm I misread world line as gate somehow. However I suppose the basic idea still stands.
Right, presumably thin only at the gate oxide portion under the floating body in the diagram.
 
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