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Let's say that an automotive chip manufacturer has a small low-cost mixed-signal design that's been out there for a few years, manufactured on a TSMC 180nm process, and it's successful. Demand goes up and now the problem is capacity constraint.
Someone points out to them that it looks like another feature size will have capacity much sooner than 180nm... say 40nm or 65nm.
What, if any, are the technological issues preventing the 180nm chip from being made as-is on a 40nm or 65nm process, to provide extra capacity?
(Economic issues are a separate nail in the coffin: maybe the cost per unit area is 2-3x as much on those smaller process nodes and it makes no sense, but humor me for a second.)
Each foundry process has a Process Design Kit (PDK) that is unique, and migrating from 180nm to a smaller process node requires engineering work like: functional simulation, logic synthesis using a new cell library, buying and integrating new 3rd party IP blocks, floor planning, standard cell place and route, design rule checking, layout versus schematic checking, parasitic extraction, static timing analysis, IR drop analysis, SPICE circuit simulations, transistor sizing for custom design and analog blocks, package selection and simulation, ATPG, and once silicon comes back from the foundry there is silicon debug and bring up, and possible re-spins in order to meet specifications. This process also requires purchasing a new mask set, and the smaller the process node the more expensive. Competent chip companies do a detailed ROI analysis before migrating from 180nm to another node.
I understand that migrating a design the regular way is a nontrivial process, but that wasn't my question; I wanted to know if a particular physical design could be manufactured on a smaller process: that is, the particular pattern of silicon and interconnects could be reproduced as is on a smaller geometry. (At least on a larger-than-FinFET node.)
I'm assuming at least the masks might have to change because of optical differences; even if the lithography wavelength is the same, unless you're at 1970s-era micron-level, the mask design must reflect geometry not only of the intended design, but would be sensitive to diffraction/distortion that is tightly coupled to the lithography equipment.
Aside from that, why can't a set of 180nm patterns be manufactured on a 40nm process?
Good point. The DRC rule deck grows by several X as you move down each smaller process node, so that's an interesting question to run a 180nm mask set on a 40nm process. I'm not sure that it would pass the DRC and ERC. Certainly the timing would change, because the smaller nodes have higher mobility values, so you're going to have to run STA and likely some SPICE runs. Back in the 1980s while working at Silicon Compilers I recall a military program going on where they wanted to help solve the issue of obsolete ICs by migrating these defunct chips to a smaller, and supported process node.
OK, thanks, that helps me get a better flavor of things. I'm guessing there's some major technological reasons (in addition to economic ones), it's just that I'm not familiar with what they are. The simplistic analogy here is a drawing where the artist runs out of ink in a 0.7mm pen and has to continue with a 0.5mm pen in its place to draw the same design, but I expect that digital IC design is a much more exacting science than just drawing lines.
(Just to clarify a bit: I'm not asking in relation to any actual design. I don't do chip design, just trying to learn more about some of the economic decisions involving semiconductors and the engineering issues that constrain/drive those decisions.)
Interesting... is that because of a characteristic vertical dimension that is smaller? or high-K gate coming into the scene at ~40-45nm? or something else?
I've been told that metal layer resistances (ohms/square) go up in lower-geometry processes because of reduced thickness, and that it primarily affects signals that travel "long" distances across-chip, but I don't have much of an idea on how that would affect things in practice.
The gate oxide is thinner for 40nm versus 180nm, which then effects the Vt of the transistor. So moving from one node to another is a complex, error prone engineering task, with entire companies setup to help you be successful in the migration.
180nm masks for 200mm wafer steppers will simply not fit into new 300mm immersion scanners. They were made for very different optical system, and use different alignment marks, so just trying to develop a mechanical adaptor for the mask holder will also not work.
Intel claims their four new leading edge fabs(2 in Arizona and 2 in Ohio) will help to resolve automobile related chips shortage.
I thought chips for automobile industry tend to use non leading edge manufacturing processes. Does Intel have some special technology to work around it or their PR just go too far?
The gate oxide is thinner for 40nm versus 180nm, which then effects the Vt of the transistor. So moving from one node to another is a complex, error prone engineering task, with entire companies setup to help you be successful in the migration.
The simplistic analogy here is a drawing where the artist runs out of ink in a 0.7mm pen and has to continue with a 0.5mm pen in its place to draw the same design, but I expect that digital IC design is a much more exacting science than just drawing lines.