Will long term reliability of chips decrease with 10nm, say over 28nm chips, because electromigration ?
I might offer up two answers...
On the one hand, the answer is
"No, designers are always responsible for analyzing powerEM and signalEM, and ensuring that the design meets their product reliability targets regardless of the silicon process node." That's kind of what some of the previous comments have suggested -- the targets vary widely, based upon whether the end application is consumer, automotive, medical, mil/aero, etc.
On the other hand, there's an underlying message in your question, about the relative difficulty in achieving EM reliability targets at 10nm... And, the answer to that question is
"Yes, between 28nm and 10nm, the scaling of interconnects and the increased current density per unit area associated with FinFET devices will result in significant changes to design methods and subsequent EM analysis."
The increase in current density at 10nm will have the greatest impact on local interconnect ("M0"), low level metals (e.g., "M1" and "M2"), and especially the contacts/vias between these layers. The design variability in lithographic width/space/pitch for these layers is very limited -- unlike upper level metals, you can't simply "just make them wider".
This will manifest itself in two main areas:
(1) There will be more stringent rules from the foundry on the maximum number of fins per device, to be able to get current into and from the device through the local metal stack. (Although the distributed FinFET gate resistance is another reason to limit max_fins/device, EM will become the dominant factor.) That max_fins limit has a substantial impact throughout all facets of the methodology, from library design to wiring track allocation to signal buffering/repowering strategies. Some of the impact is already emerging, as foundation IP offerings are indeed utilizing smaller track height cell libraries.
(2) The transition from 28nm bulk to 10nm FinFET introduces an analysis issue, one that SOI designers have always needed to consider, but is new to many. The heat dissipation paths in a FinFET are much more constrained than a bulk device, and the thermal flow is increasingly toward the interconnect metals. A "self-heating" thermal analysis is required at 10nm, to estimate the local temperature increases. (Recall that the "activation" for metal migration in an interconnect is exponentially dependent upon temperature.) Previous semiwiki articles have discussed how EDA vendors are collaborating with the foundries, to incorporate thermal self-heating maps into their analysis flows.
-chipguy
