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Are there other tools? Tools from TSMC or other foundries? Do these tools analyze and fix or just analyze? I see that Synopsys marketing claims they have auto-correct algorithms, can someone confirm this? What about auto-correction for custom design? Memories? Libraries?
When in your design methodology do you run these tools? At the block level? Core level (integrating blocks and local routes)? At the full-chip level fixing problems throughout?
OPC at 28nm and 20nm is very tricky, dependent upon the data on multiple mask layers to determine the expected printed/etched shape contours. If there are lots of "new errors in block-level data" when running the checks at core-level (due to routes over blocks and to block pins), the work done previously to fix blocks may need to be re-done... yet, you simply cannot wait until full-chip integration to run these checks... an interesting dilemma.
Some EDA vendors suggest that customers interested in running their LPA tool do so as a service instead of software licensing. The reason being given is the need for excessive compute resources and expertise to interpret results. Foundries used to do LPC services as well I believe but have moved away from this at 28nm?
Quan Gan Yah, LFD is very slow, so, I don't think it can be a tool used in design house.
auto-fixing flow is not only in synopsys tool, Cadence also has this feature in LPA tool and very useful to fix some abvious routing errors.
I think all tools's auto-fixing flow can only be applied in custom design due to grid issue of digital design.
For your mentioned, muliti-mask/reticle to print one layer contour on wafer, this technology is called DPT(double patterning technology), it should only applied in 22/20nm, not 28 nm node. DPT need to patterning process to do one layer, so the through output is ver low, but it is the only valid technology due to the EUV is not ready for production.
Hello Daniel & Quan, Very Good topic and nice share... I think it would help me a lot in my work..Although I don't have much of technical details of the technology nodes, I would like to explore themso as to get more insight into this technology(OPC and LPC). You guys, being attached to the industry might help me out.Thanks Indeed.Bapi
I think you have given the reference sign-off tools for litho checking. If your focus is more on the design phase with fixing layouts, migrating designs or generating litho-friendly layouts from the start there are a bunch of other tools. Is your focus on sign-off ?
Good Morning and thanks indeed... I should say your anticipation is right towards my comment.
My focus is more of handling design issues with the layouts i.e. how to design litho-friendly routing so that the design works on to the silicon in the smaller technology nodes.
I would be very happy if you can provide me any further directions and/or tools in this context.
To do Lithographic Process Checking the design needs to go through a similar tape-out procedure as seen in the foundry. That means the design sees double patterning decomposition (if used); assist features added (if used) and then Optical Proximity Correction is applied. From this psuedo-corrected layout simulated printed contours are generated at different focus and exposure settings simulating manufacturing variation. These contours are analysed and hot spots are returned as GDS markers. When integrated with a place and route tool this may allow re-routing to avoid such hot-spots. Of course Foundries don't want to hand out this highly sensitive model and correction flow information, and so provide these utilities as encrypted blocks - or may offer this as a third party service. Mentor and Synopsys (with ASML's Brion) are the dominant OPC suppliers and have integrated their models and flows into their place and route tools. Cadence Design which does not have a leading OPC solution, bought a company called Clear Shape which uses pattern matching to approximate the results of the flow used by the foundries - perhaps trading some accuracy for speed. Foundries like to qualify as many solutions as possible - often integrated with place and route tools - to provide flexibility for their customers. Some EDA companies like to think their solution may be better if they provide the same models and correction flow as the foundries. The quality of such a tool is determined by the number of false negative (areas asking for correction which were good after all) and false positives (areas which do not ask for a fix but need it anyway) it returns. As flows and models become more complex (with assist features and double patterning) the ability for competitors to match an incumbent's OPC vendors tape-out flow will get harder. My understanding is this technique is used at the block level and often has many heuristic rules to limit inspection to known bad layouts candidates to thus to reduce the run time. Of course prevention is better than cure and additional design rules integrated into the place and route tool can go a long way to reduce litho patterning issues at the expense of some circuit density.
Thanks Chris for your valuable inputs. As my interest goes up, I would like to get more information about it like how to get a "good" model of such "patterns" so that I can think of working with it?
Is it freely available to academia?
Research papers do depict a few. Is that all? I need get a bigger picture on that.
My focus is more of handling design issues with the layouts i.e. how to design litho-friendly routing so that the design works on to the silicon in the smaller technology nodes.
I did not use all the tools I will mention so I can't comment on the usability.
If it is manual full-custom layout then the mentioned programs are the right thing to add to the flow next to DRC, LVS, PEX etc. Chris's mail is a good reference although I thought Cadence also provided model based verification and not only pattern matching based.
Another pattern matching tool I found is Nanoscope Defect Pattern Library but I doubt this tools is fit for academic use due to lack of input data.
Other tools I had in mind:
To do Lithographic Process Checking the design needs to go through a similar tape-out procedure as seen in the foundry. That means the design sees double patterning decomposition (if used); assist features added (if used) and then Optical Proximity Correction is applied. From this psuedo-corrected layout simulated printed contours are generated at different focus and exposure settings simulating manufacturing variation. These contours are analysed and hot spots are returned as GDS markers. When integrated with a place and route tool this may allow re-routing to avoid such hot-spots. Of course Foundries don't want to hand out this highly sensitive model and correction flow information, and so provide these utilities as encrypted blocks - or may offer this as a third party service. Mentor and Synopsys (with ASML's Brion) are the dominant OPC suppliers and have integrated their models and flows into their place and route tools. Cadence Design which does not have a leading OPC solution, bought a company called Clear Shape which uses pattern matching to approximate the results of the flow used by the foundries - perhaps trading some accuracy for speed. Foundries like to qualify as many solutions as possible - often integrated with place and route tools - to provide flexibility for their customers. Some EDA companies like to think their solution may be better if they provide the same models and correction flow as the foundries. The quality of such a tool is determined by the number of false negative (areas asking for correction which were good after all) and false positives (areas which do not ask for a fix but need it anyway) it returns. As flows and models become more complex (with assist features and double patterning) the ability for competitors to match an incumbent's OPC vendors tape-out flow will get harder. My understanding is this technique is used at the block level and often has many heuristic rules to limit inspection to known bad layouts candidates to thus to reduce the run time. Of course prevention is better than cure and additional design rules integrated into the place and route tool can go a long way to reduce litho patterning issues at the expense of some circuit density.
Hi, Chris: One point I need to correct, LPA is not Pattern Matching based, also model based. If you want to use pattern matching tool from cadence, I cam make the Ads.. And at OPC field, Mentor's calibre indeed dominate the marketing, But foundry shall not let only one vendor to eat the big cake. And Brion don't have the design tool, so I don't think it can benefit the design house. And the litho process checking tool normally can be applied at any level, generally is used at full chip level.
Hi, Chris: One point I need to correct, LPA is not Pattern Matching based, also model based. If you want to use pattern matching tool from cadence, I cam make the Ads.. And at OPC field, Mentor's calibre indeed dominate the marketing, But foundry shall not let only one vendor to eat the big cake. And Brion don't have the design tool, so I don't think it can benefit the design house. And the litho process checking tool normally can be applied at any level, generally is used at full chip level.
I don't know so much about Cadence's LPA, my knowledge was based on the little of what I knew about ClearShape, of course they need to create models that approximate those used in the Foundry, and perhaps some accuracy can be sacrificed as LPC is only about finding catastrophic sites not determining printed dimensions to the closest nanometer. I'm not sure I agree that Mentor's Calibre dominates the OPC market, even if they may dominate marketing.
I have had some experience with Mentor's LFD, and was impressed with its capabilities. We ran some 32nm and 22nm layouts through it, and got good feedback. Posted by Steve
Cadence LPA is the market leader in design-side model based or pattern based litho hotspot analysis, depending on the foundry used. There is no doubt about this, and LPA is also the fastest tool in the market in its class.<o></o> Design-side litho analysis uses the manufacturing and process information which the foundry provides and all the three tools Dan mentioned LPA, LFD, and LCC are qualified. The difference is that LPA has consistently been between 4-30X faster than the two other tools depending on the design style. And this is NOT pattern based! It is model based and I cannot divulge how and why LPA is faster in this forum.....<o></o> Pattern based litho verification is a new evolution of the design side litho verification at 28nm and will continue to help even with double patterning at 20nm and beyond.<o></o> Finally, do you think the process folks in the foundry don’t know what they are doing? Your comment sounds likes you know OPC inside out but your explanation of the speed advantage of LPA is not accurate and I like to point it out. I know of many customer evals where LPA found errors at 28nm which the competitive tools missed.<o></o>
Cadence LPA is the market leader in design-side model based or pattern based litho hotspot analysis, depending on the foundry used. There is no doubt about this, and LPA is also the fastest tool in the market in its class.<o></o Design-side litho analysis uses the manufacturing and process information which the foundry provides and all the three tools Dan mentioned are qualified. The difference is that LPA has consistently been between 4-30X faster than the two other tools depending on the design style. And this is NOT pattern based! It is model based and I cannot divulge how and why LPA is faster in this forum.....<o></o Pattern based litho verification is a new evolution of the design side litho verification at 28nm and will continue to help even with double patterning at 20nm and beyond.<o></o Finally, do you think the process folks in the foundry don’t know what they are doing? Your comment sounds likes you know OPC inside out but your explanation of the speed advantage of LPA is not accurate and I like to point it out. I know of many customer evals where LPA found errors at 28nm which the competitive tools missed.
Can you elaborate a bit more on your LPA's market leadership, as well as 'always faster' claims? Because without any backing, I can state exactly the same for any other tools that are on various foundries design kits!
Thanks to Daniel for initiating this Forum. Here’s a quick overview from Mentor graphics. I’ve included links to an LPC executive summary, which discusses the specific questions that Daniel has posed, and other information on our wiki page. Readers can also access a white paper co-authored with Infineon that quantifies the ROI of litho process checking at advanced nodes.
A high-level view of the key features of Calibre® LFD serves as an example of state-of-the-art litho process checking capabilities:
Accurately detects litho hotspots and provides hints for how to fix them.
Provides litho-based electrical variability analysis, i.e., models the variation in electrical behaviors due to litho variations in the shape of manufactured IC layers (transistors, vias and interconnect wires).
Integrates with all leading P&R tools to enable automatic and interactive hotspot fixing.
Supports all major foundries including TSMC, GF, SMIC, UMC, IBM, and Samsung.
Calibre LFD is currently certified at 20nm and 14nm at the foundries that are offering these nodes. It takes into account the specific double patterning techniques used at each fab and detects potential patterning overlay errors.
Mentor recommends running Calibre LFD at multiple stages in the design flow:
Standard cells and small blocks—designers should run the front-end layers (M2/M1 and below).
Routed blocks—designers should run the routing layers (M2 and up). Integration with the P&R tool is very useful because it allows for automatic detection and repair of hotspots without the designers needing to review and figure out how to fix the hotspots.
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