The gate patch CDs are somewhat relaxed compared to other 7nm process nodes, but still shrunk compared to SMICs N+1 version. This suggests the gate density is less versus other 7nm devices in the market. However, with other design-technology co-optimization (DTCO) features implemented on this die, like single diffusion break (SDB).the gate density gap is reduced.
Lower metal layers feature similar routing strategies to SMIC's N+1 version, but with smaller CDs bring this SMIC N+2 process closer to other 7nm nodes. These enhancerments enabled SMIC to shrink its standard cell height (-5%) and standard cell area (-10%) compared to its N+1 implementation.
Discovering a Kirin 9000s chip uting SMIC's 7nm (N+2) foundry process in the new Huawei Mate 60 Pro smartphone demonstrates the technical progress China's semiconductor industry has been able to make without EUV lithography tools.
View attachment 1419