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Is there a process node for advanced packaging?

techcossack

New member
I was reading an article about TSMC's challenges in advanced packaging, their VP explained that "when it comes to advanced packaging, it is still stuck at 2μm...cost control and efficiency become a hurdle when TSMC uses frontend equipment, such as those for copper interconnect process, to facilitate heterogeneous integration."

This part confuses me...what does the 2μm refer to here? As I understand, heterogenous integration basically integrates various chips of different nodes, so this doesn't make much sense to me. Article is below

 

Paul2

Active member
I was reading an article about TSMC's challenges in advanced packaging, their VP explained that "when it comes to advanced packaging, it is still stuck at 2μm...cost control and efficiency become a hurdle when TSMC uses frontend equipment, such as those for copper interconnect process, to facilitate heterogeneous integration."

This part confuses me...what does the 2μm refer to here? As I understand, heterogenous integration basically integrates various chips of different nodes, so this doesn't make much sense to me. Article is below


It is the node for interposer, or rdl layer
 

Fred Chen

Moderator
Interposers are so wide, in order to cover two chips, that they may need two masks (stitched together), to pattern each layer. The design rules are really wide, though, as already mentioned.
 
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