simguru
Member
As a mixed-signal simulator guy, one of my goals in developing Verilog-AMS was to enable a mixed-signal IP delivery flow, where IP design houses developing parts like PLLs could provide behavioral models of their designs and and black-box GDSII (just contact/peritheral info) over the web for free to prospective customers - a "try before you buy approach". A key element of this approach was enabling back annotation for Verilog-AMS, which (as yet) has not happened.
I bring this up now because the development of Verilog-AMS and SystemVerilog is converging at the IEEE (P1800), and there also a discrete modeling effort (SV-DC) in progress to add more event-driven analog-like modeling to SystemVerilog. So if you want to help enable the above mentioned methodology, now is the time to sign up for the IEEE-SA join the relevant committees and vote for it (or vote against things that won't get us there).
Without end-user participation to drive the requirements to enable the flows we need SystemVerilog is unlikely to support easy delivery of hard IP for a very long time. There is a good chance your company is a member entity of IEEE-SA already, and if you are not represented now is the time to send someone.
IEEE SA - P1800 - Standard for System Verilog--Unified Hardware Design, Specification, and Verification Language
IEEE-SA - Corporate Channel Corporate Members
I bring this up now because the development of Verilog-AMS and SystemVerilog is converging at the IEEE (P1800), and there also a discrete modeling effort (SV-DC) in progress to add more event-driven analog-like modeling to SystemVerilog. So if you want to help enable the above mentioned methodology, now is the time to sign up for the IEEE-SA join the relevant committees and vote for it (or vote against things that won't get us there).
Without end-user participation to drive the requirements to enable the flows we need SystemVerilog is unlikely to support easy delivery of hard IP for a very long time. There is a good chance your company is a member entity of IEEE-SA already, and if you are not represented now is the time to send someone.
IEEE SA - P1800 - Standard for System Verilog--Unified Hardware Design, Specification, and Verification Language
IEEE-SA - Corporate Channel Corporate Members