I wouldn't say that verilog is poor as an entry language. Do you know how to design complex async automata (not a Moore/Mealy FSM)? the entry is just a wave form. A sequence of signal transitions on the paper. You need to take this waveform as an entry, than to draw a corresponding Petri net, and then to compile it into gate netlist using special compilers like Petrify. Looks like nightmare, but this is the best known way.
I totally agree with the second part. Concerning Verilog .. I am using it for 20+ years, and still haven't seen anything better. Unfortunately.
All known simulation and STA tools are based on synchronous approach to design. Synchronous means that all transitions are finite and must be completed before the next clock will arrive. This means that simulation/STA only handle a concurrent processes in simplest way, I mean - simultaneously, dealing with small and finite parts only - and this is how they gain a performance. There is no need in a true concurrency to simulate synchronous circuit.
From the other hand, I have no idea how to simulate a really concurrent processes. Mainly because of async arbiters and their exiting metastability time. This time isn't determined and behave like Gaussian "bell-shape" distribution. So, concurrent simulation must operate with statistical data. This is a big problem, I'd say - a blocker to invent a true concurrent simulator.
Cool! I wish you luck in this interesting topic.
Btw, when was the last time when I thought about the asynchronous CPU concept, I formed two basic blockers for this task: the first one is async interface, and the second is async RAM. The problem with SRAM is well known - it cant operate below 300-400mV (by many reasons). Concerning async interfaces .. there are no of them. Except of good old VME, perhaps. But the interface must be robust enough to prevent a latch-up of async circuit (all handshake-type async circuits are very vulnerable to latch-ups). So, what I want to say - to design a async circuit isn't a problem nowadays. The real problem is - to build the surrounding for Async to allow Async to work and to keep it safe.