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Is 20nm a Half Node?

Daniel Nenni

Admin
Staff member
I would argue yes, but I'm mostly losing that argument. It is interesting to see just what the difference is between silicon dioxide gate dielectric (40nm) and high dielectric constant (28 and 20nm), on both the design and manufacturing side. Also the difference between silicon on insulator 32nm versus high dielectric constant 28 and 20nm.

View attachment 3205

IBM 14nm FinFet Wafer






GFI told me last week that Dresden Fab 1 has shipped 250k+ 32nm SOI HKMG wafers thus far, which is more than TSMC, implying that they have the needed experience to be successful at the smaller nodes.

"We consider 32/28nm as one node because the HKMG integration is the same. That's why we say our learning on 32nm translates directly to 28nm. 22/20nm is a similar situation, however the majority of the industry is adopting 20nm. That is our primary technology platform offering."

Sounds logical to me. Anybody else care to argue differently?

GLOBALFOUNDRIES Dresden Fab Ships 250,000th 32nm HKMG Wafer

32nm HKMG ramp leads foundry industry and outpaces previous ramp at 45nm node
Milpitas, Calif., March 21, 2012 – GLOBALFOUNDRIES today announced that its Fab 1 in Dresden, Germany has shipped a quarter of a million semiconductor wafers based on 32nm High-k Metal Gate (HKMG) technology. The milestone represents a significant lead over other foundries in HKMG manufacturing and carries on a long tradition of rapidly ramping leading-edge technologies to volume production.

On a unit basis, cumulative 32nm shipments for the first five quarters of wafer production are more than double that achieved during the same period of the 45nm technology ramp, demonstrating that the overall 32nm ramp has significantly outpaced the 45nm ramp, despite the integration of a number of new and complex elements in both design and process technologies.


Press Release

D.A.N.


View attachment 3206
 
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It's possibly just semantics - but it seems that since the 45/40 node the smaller of the close-spaced pairs has been the dominant partner
i.e.
350, 250, 180/(150), 130/(110), 90, 65, (45)/40, (32)/28, (22)/20
 
For the most part, the larger number is the ITRS number, and the 2nd is the "half-node". TSMC seems to have aligned along the smaller numbers (40, 28...good marketing, no?). Those doing SOI (AMD, IBM) aligned with the higher numbers. But I'll argue again that 32nm SOI is not by any stretch "lagging behind" 28nm bulk.

As 28nm is the half-node following the 32nm litho node, would an extrapolation in terms of PPA be too off-base?

The accepted bulk vs. SOI figures at the same node have always been that SOI essentially buys you a generation of PPA: 40-50% power savings, 20-30% performance boost, 10-20% area savings. ARM demonstrated this a couple years ago at the SOI Conference for 45nm partially-depleted SOI vs. 45nm bulk (see http://www.advancedsubstratenews.com/2009/12/implementing-the-45nm-soi-arm11/).

Per the ITRS roadmap, the full node after 32nm is 22nm (and, btw, they emphasize that the whole node/half-node thing is creating immense confusion in the media). Is it reasonable to guess you'd get about half the results jumping half a node? So a bulk-to-bulk half-node move you'd expect would give you about 20% power savings, 10% performance improvement, and 5% area savings? (which would still give you less than the SOI advantage at the previous full node, no? Worth noting, too, that 32nm SOI was running in volume 9 months before 28nm bulk....)

That said, an IBM alliance paper at IEDM 09, “Competitive and Cost Effective high-k based 28nm CMOS Technology for Low Power Applications” (F. Arnaud et al) seems to indicate they don't get any performance boost from 32-to-28nm bulk-to-bulk move (see figs 7 & 8) -- if you do it, it's to save area. And an IBM paper from VLSI 09, “High Performance 32nm SOI CMOS with High-k/Metal Gate and 0.149μm2 SRAM and Ultra Low-k Back End with Eleven Levels of Copper” (B. Greene, et al) does confirm they got a 20% performance boost at 32nm w/SOI vs. bulk. Of course, these two papers are apples and oranges in terms of their target apps....

When the move to FD-SOI is made, on the other hand, that will really be a game changer -- these guys (STM, STE, IBM...) are seeing some really impressive results re: performance/power, even at 28nm (which will really confuse things in the press!).
 
Because that is what is trending on SemiWiki at the moment, people are searching for the difference between 28nm and 20nm. That and 28nm yield information. Search is about 30% of SemiWiki traffic so trending key words and search terms should be of interest. We use these trends for blogging reference and SEO tags.

As it runs out, there is significant difference between 28nm and 20nm on both the design and manufacturing side. Hopefully this discussion can continue so we can all learn from it.

D.A.N.
 
Andy Turudic Sad - not an engineer in the bunch. NO. To double the devices at each node (a Moore's law dictate), you multiply by 0.707 (divide by square root of 2). A half node, would then be 1.5x the devices or 18nm would be the half node for 22nm (multiply by 0.816), not 20nm. That is how 32nm became a half node for 40nm. Device performance (like strained) has nothing to do with classical planar device density.
 
Judging a process by the smallest line you can etch isn't really a useful metric. The pitch between lines would be better, and the pitch at which they are cut into transistors - or something like the achievable gate density (e.g. 2-input nands/um^2). The latter is probably what will tell you whether Moore's law is holding.

It should be possible to increase the density without changing the smallest etchable dimension with improvements in other areas, so 20nm could easily be a half-node.
 
Because that is what is trending on SemiWiki at the moment, people are searching for the difference between 28nm and 20nm.
...

As it runs out, there is significant difference between 28nm and 20nm on both the design and manufacturing side. Hopefully this discussion can continue so we can all learn from it.

D.A.N.

Was 90nm a half node of 130nm ? The changes between nodes back then was much less then on current nodes but I don't think people wanted to call the nodes half nodes.

If the question is if people want to know if they should use 28nm or 20nm I agree this is a relevant question. The first question people then need to ask is the price of the mask set (e.g. startup cost or NRE cost). I think this will already decide for most mortals here on the site that it won't be either 28nm or 20nm :) (we're talking about 7-digit numbers here).
Secondly I would look for the nodes which get better long term support; e.g. for TSMC you would go for 40nm or 28nm and not resp. 45nm or 32nm.

greets,
Staf.
 
ITRS

Was 90nm a half node of 130nm ? The changes between nodes back then was much less then on current nodes but I don't think people wanted to call the nodes half nodes.

If the question is if people want to know if they should use 28nm or 20nm I agree this is a relevant question. The first question people then need to ask is the price of the mask set (e.g. startup cost or NRE cost). I think this will already decide for most mortals here on the site that it won't be either 28nm or 20nm :) (we're talking about 7-digit numbers here).
Secondly I would look for the nodes which get better long term support; e.g. for TSMC you would go for 40nm or 28nm and not resp. 45nm or 32nm.

greets,
Staf.

It's perhaps worth remembering that at least technically, nodes are determined by the ITRS -- the International Technology Roadmap for Semiconductors, a worldwide industry organization. See ITRS Home. While they update it every year, they only do major rewrites every couple of years. This year is an "update" year -- details were release a couple months ago. The folks at Future Fab did a really nice job sorting it out -- see the ITRS website for a link to their work on this. BTW, it's enlightening to look at the old roadmaps -- like from 2000. Also, 130nm (2001) and 90nm (2004) were separate nodes. Things started getting messy at 60/65nm.
 
Dan:

Although this discussion thread has died down, I'm not sure you got the answer you were seeking. Here's a brief history, and (hopefully) conclusive argument. :)

The net is:

There really is no concept of a process generation "half-node" any longer, using the original definition of a half-node as a 0.9x lithographic shrink. A half-node process offering enabled a mid-production life product update, with minimal design investment. The primary goal of the half-node process was as a cost-reduction, not a performance improvement. (Power was not a major design constraint, at the time. :)

So, 20nm is not a half-node of another process technology -- it is a conscious decision by the foundries to define lithographic design rules that are not derived by scaling.

Background

The term "half-node" originated back in the 90's, when lithographic improvements were readily achievable, using the current exposure systems. A "full-node" technology transition was indicated by a 0.7x linear shrink from the previous process node, as was mentioned in this thread. A "half-node" was associated with a 0.9x linear shrink. (An earlier post in this thread had this factor incorrect).

To wit, the "full" node transitions were: 0.35um -> 0.25um -> 180nm -> 130nm -> 90nm -> 65nm -> 45nm

For these processes, the ASIC houses + fabs may have offered a "low cost" 0.9x linear shrink. Manufacturing costs were kept low, as the shrink was achieved through reduction adjustments during mask alignment and exposure -- no new mask set required.

Design costs were kept low, as minimal re-analysis of existing designs was required -- since performance was unchanged, only "short path" timing using updated clock distribution analysis was required. (Packages had to be re-designed -- see below.)

The key was that the fab was able to develop design rules for the full node with the expectation that an (all-layer) optical shrink of 0.9X would be pursued 18-24 months later.

The key for the ASIC library provider was that critical circuits (SRAM's, I/O's, PLL's) would also be robust, in the half-node shrink -- and, that models for the half-node technology could be easily generated and qualified. (The growing dependence upon pre-qualified IP, especially analog SERDES IP, made the potential for a shrink with robust circuit design much more difficult.)

The key for the packaging technology industry was to enable the bond-pad/solder-ball spacing to likewise scale.

About the time of the introduction of 90nm, the ability for foundries to develop a full-node lithography design rule set that was competitive, and also 0.9x scalable, became much more difficult. Line spaces and widths were challenges for scaling, but extensions and overlaps were extremely difficult, not to mention the increasing number and complexity of corner-to-corner and run-length based design rules. The growing dependence upon OPC and RET techniques by the mask house also introduced more uncertainty into the expectation that a full node design rule set could scale.

With the transition to the 45/40nm process node, some fabs opted to drop the "0.9x scaling" feature altogether, and focus on optimizing a single lithographic design rule set. For example, TSMC's roadmap has followed the 40nm -> 28nm -> 20nm -> 14nm progression, a 0.7x full node-like roadmap, starting with the old 40nm half-node. Other fabs have stayed with 45nm -> 32nm -> 22nm -> 15nm roadmap. (Another post in this thread correctly stated that the key measure is the contacted device and metal layer "pitches" chosen for the circuit libraries, as opposed to the minimum drawn gate length.)

So, a long way of saying, there is no "half node" any longer. Design groups are not expecting to leverage a 0.9x mid-life shrink, as a cost reduction. The production cost models for a new design project should be based upon the fab's wafer cost projections and defect-density (process-limited yield) projections over the anticipated product lifetime, at the (original) process node.

Hope this helps somehow.

-chipguy
 
With the transition to the 45/40nm process node, some fabs opted to drop the "0.9x scaling" feature altogether, and focus on optimizing a single lithographic design rule set.

I think saying they opted to drop the 0.9x scaling is a (too) nice way of saying things. IMO they were too late with the main node so they had to switch to the half node to keep on the scaling tread mill. As far as I remember TSMC had both 45 and 32nm nodes but highly advised customers to use the half node version.

greets,
Staf.
 
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