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Interlaken IP Core for high-speed chip-to-chip applications is now available


Staff member
Copenhagen, Denmark, September 29, 2021 - Comcores ApS, a fast-growing specialized supplier of Intellectual Property (IP) Cores expands its Chip-to-chip interface IP portfolio by announcing the availability of a high-performance Interlaken IP.

Comcores as the leading provider of silicon-proven JESD204B and JESD204C Controller IPs, now introduces a high-performanze Interlaken IP, a silicon and PHY agnostic implementation of the Interlaken Protocol version 1.2 targeting any ASIC or FPGA technologies.

Key Benefits of the Interlaken IP;

High Performance

- up to 2.6Tbps maximum bandwidth 48 lanes
- up to 56Gbps SerDes per lane

- MAC layer with fast AMBA CXS interface and highly configurable PCS layer
- flow control, dual calender, look-aside, retransmit, and FEC support as options

- Gearbox included to enable easy interfacing to any SerDes width
- Extensive feature-set and option to customize based on customers' need

Easy to use
- Strong engineer support for bring-up
- easy to use RTL test environment

About Comcores

Comcores is a Key supplier of digital IP Cores and design services for digital subsystems with a focus on Ethernet Solutions, Wireless Fronthaul and [-RAN, and Chip to Chip Interfaces. Comcores’ mission is to provide best-in-class, state of the art, quality components and design services to ASIC, FPGA, and System vendors, and thereby drastically reduce their product cost, risk, and time to market. Our longterm background in building communication protocols, ASIC development, wireless networks and digital radio systems has brought a solid foundation for understanding the complex requirements of modern communication tasks. This know-how is used to define and build state-of-the-art, high-quality products used in communication networks.

To learn more about this solution from Comcores, please contact us at or visit