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Intel "Years Ahead" in Packaging Technologies?

prime007

Active member
During an interview with Yahoo! Finance (linked below starting with Pat's statement on Intel's capabilities), new Intel CEO Pat Gelsinger claimed that companies should leverage them as a foundry because they can do "some things that can't be done anywhere else in the world". He specifically pointed out "system unpackaged technologies" (I'm assuming he's actually referring to Intel's packaging technologies here...EMIB & Foveros).

Semiconductors are not my expertise...so I'm curious if the forum members here would agree with Pat and view Intel's packaging technology as superior to both TSMC's 3DFabric and Samsung's...or is he just marketing/hyping up Intel for investors?
 

hskuo

Active member
This report from Yole might help answer part of your questions. Besides, tsmc announced ~10% of 2021 CapEx($25-28B) will be in advanced packages. Not sure how much will intel spend in his $20B CapEx for advanced package foundry.
1616919493497.png

 

Paul2

Active member
During an interview with Yahoo! Finance (linked below starting with Pat's statement on Intel's capabilities), new Intel CEO Pat Gelsinger claimed that companies should leverage them as a foundry because they can do "some things that can't be done anywhere else in the world". He specifically pointed out "system unpackaged technologies" (I'm assuming he's actually referring to Intel's packaging technologies here...EMIB & Foveros).
Lets have TSMC packaging guys comment on this...

Saying this, first what you want to ask is "Years ahead in what kind of packaging?"

TSMC is years ahead in mobile package formats fore sure. Some HPC, and a lead in interposer packaging. WLCSP? TSMC too. High-end RDL? TSMC.

Intel... EMIB? Optics?
 

Rstar

New member
Having invented EmIB for Intel before I retired 5 years ago to cost effectively connect disparate high density IO from different dice on a package I maybe be biased. But I'd say it is a huge packaging cost and complexity advantage when using mixed fab technologies and manufacturers. Foveros is chip on chip stacking with thru silicon vias, and the combination of stacked die with other chiplets has a significant yield and cost advantage over silicon interposer or reconstructed wafer packaging.

Whether Intel can convince customers to let them combine their proprietary IP (assuming their design tools are no longer so difficult to use and designs are no longer constrained by onerous fab design rules) and whether Intel's manufacturing strength as a high volume/low mix company, can work for low volume/high mix custom chips is the biggest question for me.
 

Paul2

Active member
Having invented EmIB for Intel before I retired 5 years ago to cost effectively connect disparate high density IO from different dice on a package I maybe be biased. But I'd say it is a huge packaging cost and complexity advantage when using mixed fab technologies and manufacturers. Foveros is chip on chip stacking with thru silicon vias, and the combination of stacked die with other chiplets has a significant yield and cost advantage over silicon interposer or reconstructed wafer packaging.

Whether Intel can convince customers to let them combine their proprietary IP (assuming their design tools are no longer so difficult to use and designs are no longer constrained by onerous fab design rules) and whether Intel's manufacturing strength as a high volume/low mix company, can work for low volume/high mix custom chips is the biggest question for me.
Is EMIB than much cheaper than a whole uncut interposer? I believe they don't use high grade wafers for them.
 

Rstar

New member
Is EMIB than much cheaper than a whole uncut interposer? I believe they don't use high grade wafers for them.
With emib there is only dense (for packaging) routing in the chip to chip interconnect area using coarse patterned Si or glass chiplets embedded in the package. The interconnect chiplets is similar to an interposer, but only the size of the dense io routing.
 

hskuo

Active member
Having invented EmIB for Intel before I retired 5 years ago to cost effectively connect disparate high density IO from different dice on a package I maybe be biased. But I'd say it is a huge packaging cost and complexity advantage when using mixed fab technologies and manufacturers. Foveros is chip on chip stacking with thru silicon vias, and the combination of stacked die with other chiplets has a significant yield and cost advantage over silicon interposer or reconstructed wafer packaging.

Whether Intel can convince customers to let them combine their proprietary IP (assuming their design tools are no longer so difficult to use and designs are no longer constrained by onerous fab design rules) and whether Intel's manufacturing strength as a high volume/low mix company, can work for low volume/high mix custom chips is the biggest question for me.
EMIB is smart design to leverage high density IO interconnect in smaller chip comparing to interposer. It will be very interesting to see what will be the standard of interconnect PHY eventually? intel's AIB, MDIO, tsmc's Lipincon, AMD's IFOP or others.
 

Jimlei

New member
On one hand they are trying to use more TSMC or Samsung, on the other hand they are trying to steal their customers... Doesn't sound logical to me... Felt this guy is not down to earth. What do you think?
 

Rstar

New member
On one hand they are trying to use more TSMC or Samsung, on the other hand they are trying to steal their customers... Doesn't sound logical to me... Felt this guy is not down to earth. What do you think?
I don't exactly know the situation since I've been gone for a while, but Intel used tsmc modems and in servers Samsung (probably) memory. With Google, microsoft, and amazon designing their own accelerator chips, someone like tsmc or Samsung is making them. Intel will be able to leverage that experience and incorporate them with their silicon through foveros and emib. I think those customers trying to do custom server chips are in over their heads and could leverage Intel here.
 

Daniel Nenni

Admin
Staff member
Lets have TSMC packaging guys comment on this...

Saying this, first what you want to ask is "Years ahead in what kind of packaging?"

TSMC is years ahead in mobile package formats fore sure. Some HPC, and a lead in interposer packaging. WLCSP? TSMC too. High-end RDL? TSMC.

Intel... EMIB? Optics?

We are working on it. It really is a tough comparison. Intel specific packaging versus TSMC packaging for different verticals.
 

ChrisGar

Member
Having invented EmIB for Intel before I retired 5 years ago to cost effectively connect disparate high density IO from different dice on a package I maybe be biased. But I'd say it is a huge packaging cost and complexity advantage when using mixed fab technologies and manufacturers. Foveros is chip on chip stacking with thru silicon vias, and the combination of stacked die with other chiplets has a significant yield and cost advantage over silicon interposer or reconstructed wafer packaging.

Whether Intel can convince customers to let them combine their proprietary IP (assuming their design tools are no longer so difficult to use and designs are no longer constrained by onerous fab design rules) and whether Intel's manufacturing strength as a high volume/low mix company, can work for low volume/high mix custom chips is the biggest question for me.
How about Intel use EMIB or Foveros for silicon made at TSMC?

I think that Intel could not use these technologies for TSMC silicon. TSMC implements advanced packaging as part of the silicon fab -- so I don't think it would be practical to have TSMC partially built silicon shipped out of TSMC.

So I think Intel would be using CoWoS (some variant) for parts made at TSMC.
 

Rstar

New member
How about Intel use EMIB or Foveros for silicon made at TSMC?

I think that Intel could not use these technologies for TSMC silicon. TSMC implements advanced packaging as part of the silicon fab -- so I don't think it would be practical to have TSMC partially built silicon shipped out of TSMC.

So I think Intel would be using CoWoS (some variant) for parts made at TSMC.
I'm not positive, but I think Intel already uses TSMC for foveros like parts and HBM with Samsung for emib
 

hskuo

Active member
How about Intel use EMIB or Foveros for silicon made at TSMC?

I think that Intel could not use these technologies for TSMC silicon. TSMC implements advanced packaging as part of the silicon fab -- so I don't think it would be practical to have TSMC partially built silicon shipped out of TSMC.

So I think Intel would be using CoWoS (some variant) for parts made at TSMC.
This answers your question. Yes, intel does use tsmc chips in chiplet portfolio.
1617052868029.png
 
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