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Intel to Focus on Truth and Transparency!

Daniel Nenni

Admin
Staff member
Honesty and transparency can go a long way in the semiconductor industry, just ask TSMC. This is for the greater good, absolutely. Non transparent semiconductor companies are now on notice. Follow the leaders or suffer the slings and arrows of outrageous misfortune.

Bob Swan, Intel CEO, Fortune's Brainstorm Tech conference in Aspen, Colo.

"[The delay was] somewhat a function of what we've been able to do in the past, which in essence was defying the odds. At a time when it was getting harder and harder, we set a more and more aggressive goal. From that, it just took us longer."

"The short story is we learned from it. The next generation of manufacturing improvements will be ready in about two years. Intel is internally emphasizing greater sharing of information between units. The goal is to pull entire company together through more truth and transparency and the free flow of information."


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ugotownedo

New member
Daniel, could you explain how the design rules are affected by mask/layer count? In Scotten Jones' article "TSMC and Samsung 5nm Comparison," the tables show TSMC's total layer count dropping from 75 at 7nm to 59 at 5nm, and I presume the numbers going from Intel's 10nm to 7nm node to be in the same ballpark. How can a ~20 - 25% reduction in layers lead to a 4x or 75% reduction in design rules?

If that's true, I think Intel will have a bonanza of products come out in 2021 (assuming a 1H2021 7nm ramp) compared to the relatively small number of SKUs I expect from 10nm.
 

Scotten Jones

Moderator
Daniel, could you explain how the design rules are affected by mask/layer count? In Scotten Jones' article "TSMC and Samsung 5nm Comparison," the tables show TSMC's total layer count dropping from 75 at 7nm to 59 at 5nm, and I presume the numbers going from Intel's 10nm to 7nm node to be in the same ballpark. How can a ~20 - 25% reduction in layers lead to a 4x or 75% reduction in design rules?

If that's true, I think Intel will have a bonanza of products come out in 2021 (assuming a 1H2021 7nm ramp) compared to the relatively small number of SKUs I expect from 10nm.
For TSMC going from 7nm to 5nm they have taken multi-patterned layers and converted them to EUV. Multi-patterned layers have multiple masks with complex mask interactions requiring complex design rules. EUV is much more straight forward from a patterning and design rule perspective.

For Intel going from 10nm to 7nm should see mask counts go from 70 to 62 masks.
 

Daniel Nenni

Admin
Staff member
Daniel, could you explain how the design rules are affected by mask/layer count? In Scotten Jones' article "TSMC and Samsung 5nm Comparison," the tables show TSMC's total layer count dropping from 75 at 7nm to 59 at 5nm, and I presume the numbers going from Intel's 10nm to 7nm node to be in the same ballpark. How can a ~20 - 25% reduction in layers lead to a 4x or 75% reduction in design rules?

If that's true, I think Intel will have a bonanza of products come out in 2021 (assuming a 1H2021 7nm ramp) compared to the relatively small number of SKUs I expect from 10nm.
Not having to use multi patterning will significantly reduce design rule count. A design implementation group I spent time with went from TSMC 7nm to Samsung 7nmEUV and the only thing they could talk about was how easy it is due to the reduced design rule count.
 

count

Member
Intel's earnings, while not great, were better than expected and guidance was ok. And it was refreshing to see a lack of spin around the Apple sale. So far there hasn't been much impact from AMD's resurgence, but I think that will likely start to materialize later this year.
 

Daniel Nenni

Admin
Staff member
Just when I thought Intel had turned a corner in the truth and transparency thing:

"Both yield and defect density are ahead of schedule for our 10-nanometer data center products"

I wonder what schedule he is talking about....
 

ugotownedo

New member
For TSMC going from 7nm to 5nm they have taken multi-patterned layers and converted them to EUV. Multi-patterned layers have multiple masks with complex mask interactions requiring complex design rules. EUV is much more straight forward from a patterning and design rule perspective.

For Intel going from 10nm to 7nm should see mask counts go from 70 to 62 masks.
Ah ok I see, so design complexity doesn't scale linearly with the number of layers. Going from a quad-patterned layer to single EUV won't just be a 75% reduction, but more because of the inter-mask dependencies (I'm guessing alignment is the biggest challenge here) of multi-patterning being eliminated. Thanks!
 

ugotownedo

New member
Not having to use multi patterning will significantly reduce design rule count. A design implementation group I spent time with went from TSMC 7nm to Samsung 7nmEUV and the only thing they could talk about was how easy it is due to the reduced design rule count.
That's great news. A common concern brought up at semiengineering.com is that fewer and fewer customers can afford to design for the latest node. But now it seems design cost will stay flat for the next ~5 years as EUV replaces more multi-patterned layers.

Is it only quad-patterning DUV that EUV is now competitive against, or could it displace triple or even double-patterning over the next few years? I know DUV tools are still getting better too (at a much slower rate than EUV though, being a mature technology) so maybe the gap will always remain too large from EUV to take over completely.
 

ugotownedo

New member
Just when I thought Intel had turned a corner in the truth and transparency thing:

"Both yield and defect density are ahead of schedule for our 10-nanometer data center products"

I wonder what schedule he is talking about....
The revised schedule+++ :)

All that probably means is the datacenter ramp up volumes will be a month or two ahead of most recent expectations. AFAIK they only only specified a broad 2020H1 launch, 2020H2 HVM.
 

hist78

Member
The revised schedule+++ :)
The revised revised revised ~ schedule.

Also, Bob Swan said: "Intel is internally emphasizing greater sharing of information between units. "

That sounds very strange for a leader in the information technology industry. Is Intel in a much serious situation than we thought?
 
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