Intel Says It’s on Course to Regain Chip Production Leadership

[Daniel Nenni]

Intel is currently mass producing 7-nanometer chips. It is ready to start manufacturing 4-nanometer semiconductors and will be ready to move to 3 nanometers in the second half of 2023,

"Intel Corporation is taking a far more pragmatic approach than in the past, building in contingency plans to make sure there are no more major delays. It’s also relying more on equipment vendors for help, rather than trying to do all of the work itself" Ann Kelleher.

Intel Says It’s on Course to Regain Chip Production Leadership

Intel Corp. is hitting all the targets it has set on a path to regain leadership in semiconductor manufacturing, according to the executive responsible for the effort.

www.bloomberg.com

 

[Daniel Nenni]

Intel will have to wait for GAA to retain the lead which is a distinct possibility but TSMC and Samsung will not be running in place. GAA is an exciting race!

 

[Mooredaddy]

Intel will have to wait for GAA to retain the lead which is a distinct possibility but TSMC and Samsung will not be running in place. GAA is an exciting race!

Hey Daniel, do you know how GAA implementation is going at TSMC on N2 and beyond? Are they running into difficulties/ are significant performance uplifts occurring or expected?

 

[nghanayem]

Daniel has a better ear for this stuff, but I've only heard they are doing fine (same issues everyone has to deal with). I would be more worried about whatever is after N2 getting delayed from all of the extra attention N3 needed. A more concerning trend is the current roadmap (N2 risk starts end of 2024 to early 2025), as well as the statement that after N2 they are going to a 3 year cadence (probably not a TSMC exclusive problem). Until I see evidence to the contrary TSMC has earned absolute faith in their roadmaps. Another perplexing thing is that TSMC said that N2 would "offer support for a backside power distribution network". To me this says a non design compatible nodelet. You either support it or you don't, as it makes a massive difference to the process flow. Will this nodelet come out with the initial N2? Or does it come a year latter and have to compete with what will probably be even stiffer foundry competition?

 

[Daniel Nenni]

Hey Daniel, do you know how GAA implementation is going at TSMC on N2 and beyond? Are they running into difficulties/ are significant performance uplifts occurring or expected?

Based on what TSMC said at OIP N2 is going as scheduled. Inside the ecosystem however it has been very quiet. A lot of the IP is made available based on customer demand and big customers make most of their own IP so this is not unusual.

It really comes down to ROI. Will TSMC N3 keep pace with Intel 18A and Samsung 3/2nm in regards to power/performance/density/cost? And what are the design switch over costs and risks associated with GAA?

In my opinion N2 will be a learning node with most customers sticking with N3x FinFET for as long as possible, except of course Apple, AMD, Nvidia and Qualcom who touch every node possible. Even so, N3 will be the biggest FinFET foundry node ever, absolutely.

 

[Mooredaddy]

Based on what TSMC said at OIP N2 is going as scheduled. Inside the ecosystem however it has been very quiet. A lot of the IP is made available based on customer demand and big customers make most of their own IP so this is not unusual.

It really comes down to ROI. Will TSMC N3 keep pace with Intel 18A and Samsung 3/2nm in regards to power/performance/density/cost? And what are the design switch over costs and risks associated with GAA?

In my opinion N2 will be a learning node with most customers sticking with N3x FinFET for as long as possible, except of course Apple, AMD, Nvidia and Qualcom who touch every node possible. Even so, N3 will be the biggest FinFET foundry node ever, absolutely.

I’ve heard a very minimal amount about N2 so I’m glad to get your input. I imagine we’ll hear more about N2 in January at the earliest. Because N2 is yield learning I guess their isn’t much incentive to use it until TSMC is finalizing what the commercial successor to it will be. Would love to get some longer term roadmaps from TSMC but I’ll guess we’ll have to wait.

 

[Daniel Nenni]

I’ve heard a very minimal amount about N2 so I’m glad to get your input. I imagine we’ll hear more about N2 in January at the earliest. Because N2 is yield learning I guess their isn’t much incentive to use it until TSMC is finalizing what the commercial successor to it will be. Would love to get some longer term roadmaps from TSMC but I’ll guess we’ll have to wait.

The next TSMC Symposium will be the time and place for sure, April 2023.

 

[Mooredaddy]

Daniel has a better ear for this stuff, but I've only heard they are doing fine (same issues everyone has to deal with). I would be more worried about whatever is after N2 getting delayed from all of the extra attention N3 needed. A more concerning trend is the current roadmap (N2 risk starts end of 2024 to early 2025), as well as the statement that after N2 they are going to a 3 year cadence (probably not a TSMC exclusive problem). Until I see evidence to the contrary TSMC has earned absolute faith in their roadmaps. Another perplexing thing is that TSMC said that N2 would "offer support for a backside power distribution network". To me this says a non design compatible nodelet. You either support it or you don't, as it makes a massive difference to the process flow. Will this nodelet come out with the initial N2? Or does it come a year latter and have to compete with what will probably be even stiffer foundry competition?

The billion dollar questions right there friend. I swear the questions on TSMC’s earnings calls should come from those on this forum and not these surface level Wall Street analysts. Every quarter valuable time
is wasted on the same useless questions from the finance community who are seemingly unable to see the forest from the trees, where as I’d love to get just one question in with CC.

 

[Fred Stein]

Intel is currently mass producing 7-nanometer chips. It is ready to start manufacturing 4-nanometer semiconductors and will be ready to move to 3 nanometers in the second half of 2023,

"Intel Corporation is taking a far more pragmatic approach than in the past, building in contingency plans to make sure there are no more major delays. It’s also relying more on equipment vendors for help, rather than trying to do all of the work itself" Ann Kelleher.

Intel Says It’s on Course to Regain Chip Production Leadership

Intel Corp. is hitting all the targets it has set on a path to regain leadership in semiconductor manufacturing, according to the executive responsible for the effort.

www.bloomberg.com

I'm curious if there is a comparison of Intel's major projections about new process and actual results since Pat took over. I'm in no position to judge Pat. The question is about changing a large disparate organization. And, yes, nearly everyone misses milestones.

 

[nghanayem]

I'm curious if there is a comparison of Intel's major projections about new process and actual results since Pat took over. I'm in no position to judge Pat. The question is about changing a large disparate organization. And, yes, nearly everyone misses milestones.

Nothing could have changed that we have visibility to other than doubling and tripling down on intel’s fabs. The former 7nm, 5nm, SPR, mtl, ect were already defined and had large portion of the work done before Pat rejoined the company. We won’t begin to know the results of intel’s new culture campaign until we see 20/18A on time, as well as ARL (and it’s server equivalent) on time. You could even argue that we won’t know until we see intel’s next major node (after 20/18A)/products on it. Since these projects will be defined 100% during Pat’s watch and should be the first products designed for the new Tick-Tock model. As opposed to the current roadmap projects where they are either too late to change methodologies (saphire rapids and the years of 7nm delays), or the new mindset can only be partially adopted (derisking 20A back side power with an i3 test platform and introducing half nodes/starting with the HP library for i4).

 

[lefty]

I was just reading an interesting article at angstronomics. They say:
"Intel 4 is also an incomplete node, only offering a single 3-fin library and a minimal I/O library for chiplet-only interconnect to accelerate Time-To-Market (TTM). (https://www.angstronomics.com/p/the-truth-of-tsmc-5nm)"

This makes sense as otherwise why would Intel use both Intel 4, TSMC 6nm and TSMC 5nm chiplets in Meteor lake.
I wonder if they will do something similar for Intel 3 and save all their resources for Intel 20A.

 

[nghanayem]

Intel 3 is the full node. IO fins, HD library, and the like. As well as a few enhancements like a full node performance uplift, more euv, and whatever “denser libraries” means. Think of 4 as the LPE version, and 3 as the LPP version. A better question would be if 20A and 18A have a similar relationship, or is 20A is a complete node?

As for using non intel silicon for the gfx and soc, this lets intel ramp their product stack way faster. You can fit a bit more than 5 mtl cpu tiles in the space of an adl mobile die (based on die size estimates from when intel was showing off mtl at some conference). Given the limited capacity intel will have at first, this lets them “cheat” out more cpus than their capacity would otherwise allow. GPU wise intel 7 has a worse cost structure than N6 (probably worse density too), combine this with their graphics architecture already being on N6 and I see no reason not to use TSMC for these bits.

 

[cliff]

Samsung/Intel: Low-power early (first gen), low-power plus and low-power ultimate.

TSMC: General purpose (G), low-power (LP), high-performance (HP), high-performance mobile (HPM), high-performance compact (HPC)

3 fins... That's what we make first. Good enough.

 

[nghanayem]

Samsung/Intel: Low-power early (first gen), low-power plus and low-power ultimate.

TSMC: General purpose (G), low-power (LP), high-performance (HP), high-performance mobile (HPM), high-performance compact (HPC)

3 fins... That's what we make first. Good enough.

I’m sure intel will eventually give us a 4 fin device so they can make a desktop mtl chip that burns 300W

 

[lefty]

The U-series would suffer with the chiplet architecture, because it uses more power. This is the reason that AMD don't use chiplets for their mobile processors (up til now neither did Intel)

Intel 3 is the full node. IO fins, HD library, and the like. As well as a few enhancements like a full node performance uplift, more euv, and whatever “denser libraries” means. Think of 4 as the LPE version, and 3 as the LPP version. A better question would be if 20A and 18A have a similar relationship, or is 20A is a complete node?

As for using non intel silicon for the gfx and soc, this lets intel ramp their product stack way faster. You can fit a bit more than 5 mtl cpu tiles in the space of an adl mobile die (based on die size estimates from when intel was showing off mtl at some conference). Given the limited capacity intel will have at first, this lets them “cheat” out more cpus than their capacity would otherwise allow. GPU wise intel 7 has a worse cost structure than N6 (probably worse density too), combine this with their graphics architecture already being on N6 and I see no reason not to use TSMC for these bits.

I've heard 20A is not a complete node (which is probably why Arrow lake is using TSMC N3 chiplets)

 

[Daniel Nenni]

The U-series would suffer with the chiplet architecture, because it uses more power. This is the reason that AMD don't use chiplets for their mobile processors (up til now neither did Intel)
I've heard 20A is not a complete node (which is probably why Arrow lake is using TSMC N3 chiplets)

Intel 20A is a yield learning node. There are no IOs etc... to make a full chip. It is for CPU chiplets only. The other chiplets on the Intel chips will be made by TSMC. Notice that Intel calls them chiplets now instead of tiles. Progress!

So for those people who are comparing Intel 20A to Intel N3 or N2 it is not a fair comparison. TSMC has to make full chip SoCs for Apple during their yield learning phase not just a chiplet. Compare Intel 18A which is the foundry version of Intel GAA which will in fact do full chips.

 

[nghanayem]

Intel 20A is a yield learning node. There are no IOs etc... to make a full chip. It is for CPU chiplets only. The other chiplets on the Intel chips will be made by TSMC. Notice that Intel calls them chiplets now instead of tiles. Progress!

So for those people who are comparing Intel 20A to Intel N3 or N2 it is not a fair comparison. TSMC has to make full chip SoCs for Apple during their yield learning phase not just a chiplet. Compare Intel 18A which is the foundry version of Intel GAA which will in fact do full chips.

Why do we even call them chiplets? As far as I know IBM just called each one a die that was part of an MCM design.

 

[Xebec]

Why do we even call them chiplets? As far as I know IBM just called each one a die that was part of an MCM design.

That is true. I'm curious too as 10 years ago this would be equivalent to CPU only vs SoC.

 

[blueone]

Why do we even call them chiplets? As far as I know IBM just called each one a die that was part of an MCM design.

Intel technically calls them tiled dies, and has for over a decade. EE Times claims the chiplet term was in use since 1969. I think a lot of press and marketing people just think the term chiplet sounds cool.

https://www.eetimes.com/chiplets-a-short-history/

 

[cliff]

Chiplets are the child die that flipchips to the parent die