@Artificer60 , your math is interesting, but I think your proximal cause, lack of automation, is off. My view is that the extra headcount stems from 3 sources:
* The inherent inefficiency of the IDM model when all your products require near-leading-edge processes to be competitive. Intel, the IDM, had very few ways to continue to monetize their fully depreciated fabs that were essentially paid for, but no longer useful to them. The headcount for a fab is very front-end loaded for process and IP development, plus bring up, but an operating yielding fab is very automated. About half of TSMCs revenue, and I would guess 3/4 or more of their wafer capacity comes from essentially mature processes and customer designs - very “cheap” when it comes to headcount vs wafer starts. The numbers are quite different for Intel.
* Combine that with scale - I think I did a back of envelop calculation that TSMC was doing 1.3x the number of leading edge wafers that Intel was doing. So TSMC is amortizing the headcount of process and IP development as well as process bring up over substantially more wafers.
* Intel’s go it alone fab equipment, process, IP and design methodology strategy. The outside foundry ecosystem has far greater scale and offers far better shared resource efficiencies that Intel the IDM never wanted to avail themselves of for fear of giving up their secrets and competitive edge.