Intel Meteor Lake delayed to the end of 2023

[Maximus]

Embracing Chaos: The Imperfect Art of Semiconductor Manufacturing And Lithography

5 Longs, Intel EUV Delayed Again, And More

www.semianalysis.com

Quote:
"Intel has also confidentially stated that they are manufacturing ready for
EUV lithography in their Intel 4 process node. We don’t really believe them
because internal documents we obtained show Intel’s first high-volume
product utilizing EUV, Meteor Lake, has been delayed yet again, with “
ready-to-ship” dates delayed until Week 52, 2023 at minimum."

The author Dylan Patel added a comment on his Twitter:
"MTL-P is what's being talked about in the report.
Both U and H are even later than that date.
None is talking about S here."

 

[lefty]

I think they will get away with a delay of 6 months. It's pretty easy to hide a delay like this by just reducing the initial shipping volume. But anymore and they are in serious trouble. There are rumours of a major Xeon customer switching to AMD if they don't deliver sierra forest in early 2024.

 

[Daniel Nenni]

Embracing Chaos: The Imperfect Art of Semiconductor Manufacturing And Lithography

5 Longs, Intel EUV Delayed Again, And More

www.semianalysis.com

Quote:
"Intel has also confidentially stated that they are manufacturing ready for
EUV lithography in their Intel 4 process node. We don’t really believe them
because internal documents we obtained show Intel’s first high-volume
product utilizing EUV, Meteor Lake, has been delayed yet again, with “
ready-to-ship” dates delayed until Week 52, 2023 at minimum."

The author Dylan Patel added a comment on his Twitter:
"MTL-P is what's being talked about in the report.
Both U and H are even later than that date.
None is talking about S here."

This is a source you trust? You do realize this gentleman has zero semiconductor education or experience.

 

[Maximus]

I think they will get away with a delay of 6 months. It's pretty easy to hide a delay like this by just reducing the initial shipping volume. But anymore and they are in serious trouble. There are rumours of a major Xeon customer switching to AMD if they don't deliver sierra forest in early 2024.

I guess you're referring to this:

The original designs of Sierra Forest contain 512 cores and 344 cores but the key customer is focusing on the model with only 144 cores.

 

[Maximus]

This is a source you trust? You do realize this gentleman has zero semiconductor education or experience.

Thanks for the reminder and I definitely take it with a grain of salt. On the other hand, Intel 4 HVM is delayed 2 quarters to 2023Q3 from another source so it would not be odd if the end of 2023Q4 is the Meteor Lake shipping time of some final products.

 

[blueone]

This is a source you trust? You do realize this gentleman has zero semiconductor education or experience.

I agree. Patel is a good writer, but not being a semiconductor engineer myself I sometimes feel the urge to fact-check what he says, and that is easier wished for than accomplished for a non-expert. I have the same issue with David Kanter:

Intel 4 Process Scales Logic with Design, Materials, and EUV

The Intel 4 process achieves 20% better performance and scales logic density by 2X while reducing costs through extensive design co-optimization, adoption of new materials, and judicious use of EUV lithography. The first product, the Meteor Lake compute tile will ramp to high volume...

www.realworldtech.com

 

[nghanayem]

On the other hand, Intel 4 HVM is delayed 2 quarters to 2023Q3 from another source so it would not be odd if the end of 2023Q4 is the Meteor Lake shipping time of some final products.

Nonsense. Take for example TSMC. At the end of the year the process is "done". In the first half of the next year production for Apple begins and the product launches in September. It takes months for wafers to run through the fab. To say nothing months to get shipped out, packaged, put in a laptop, and shipped to a bestbuy near you. If MTL launches in the second half of this year those wafers had to have been made in the first half of this year. This would be consistent with claims that "in Q4 '22 intel 4 reached HVM readiness".

 

[Daniel Nenni]

I agree. Patel is a good writer, but not being a semiconductor engineer myself I sometimes feel the urge to fact-check what he says, and that is easier wished for than accomplished for a non-expert. I have the same issue with David Kanter:

Intel 4 Process Scales Logic with Design, Materials, and EUV

The Intel 4 process achieves 20% better performance and scales logic density by 2X while reducing costs through extensive design co-optimization, adoption of new materials, and judicious use of EUV lithography. The first product, the Meteor Lake compute tile will ramp to high volume...

www.realworldtech.com

David Kanter actually knows what he is talking about but sometimes he is hard to read. And like anyone of us he can be wrong, just make sure you distinguish between fact and opinion.

 

[Tanj]

This is a source you trust? You do realize this gentleman has zero semiconductor education or experience.

He is learning fast, and building his source network fast. Still the occasional blip, but interesting reading.

 

[Daniel Nenni]

He is learning fast, and building his source network fast. Still the occasional blip, but interesting reading.

Did you see the one where he called TSMC a drug dealer?

SemiAnalysis: "TSMC, The Drug Dealer, Is Trying To Make An Addicted Junkie Out Of Intel – Wafer Supply Agreement Insights For AMD, Apple, Broadcom, Intel, MediaTek, Nvidia, and Qualcomm"

That was a blip and a half. I can assure you his TSMC sources are imaginary.

 

[blueone]

David Kanter actually knows what he is talking about but sometimes he is hard to read. And like anyone of us he can be wrong, just make sure you distinguish between fact and opinion.

At the time it was posted I had two Intel manufacturing engineers I know review the article, and they said it was pretty good too. Many of the articles on Kanter's site (which really isn't active anymore) are in areas I have direct experience, and there is a lot of Patel-like regurgitation with flourishes of company-supplied material, though I think his software expertise is considerable. I never found Kanter difficult to read. Truth be told though, I mostly read his site for the comments by his readers. Many have very deep expertise, and include some luminaries like Linus Torvalds.

 

[Daniel Nenni]

I think Dave is working full time now but I know he is still part of Hot Chips.

I understand the "fake it until you make it" business model but I do not care for it. People are misinformed during the fake it period and sometimes they do not make it.

As a result Dylan is banned from SemiWiki and I usually delete references to his posts but I let this one stand to see how it goes. Unfortunately:

"Intel has also confidentially stated that they are manufacturing ready for EUV lithography in their Intel 4 process node. We don’t really believe them
because internal documents we obtained show Intel’s first high-volume product utilizing EUV, Meteor Lake, has been delayed yet again, with“ ready-to-ship” dates delayed until Week 52, 2023 at minimum."

The problem here is that, to gain credibility, he referenced internal Intel documents that he should not have, right? Not acceptable at all.

And just to be clear, your Intel sources agree that Intel 4 is not EUV ready? If so you need better Intel sources.

 

[blueone]

And just to be clear, your Intel sources agree that Intel 4 is not EUV ready? If so you need better Intel sources.

My Intel sources were commenting on David Kanter's post, not Dylan's.

 

[Daniel Nenni]

My Intel sources were commenting on David Kanter's post, not Dylan's.

Sorry, I missed that.

https://www.linkedin.com/in/kanterd/

David Kanter is a Founder and the Executive Director of MLCommons where he helps lead the MLPerf benchmarks, datasets, and best practices. He has 16+ years of experience in semiconductors, computing, and machine learning. He founded a microprocessor and compiler startup, was an early employee at analytic database pioneer Aster Data Systems, and has consulted for industry leaders such as Intel, Nvidia, KLA, Applied Materials, Qualcomm, Microsoft and many others. He has served as a litigation consultant for >10 clients.

EducationEducation​

• 
  University of Chicago
  BS, Mathematics, Economics, Computer Science
  • • ● Graduated with honors in both Mathematics and Economics.
      ● Wrote a thesis about the economics of the semiconductor industry, focusing on technological advances (i.e. Moore's Law) and the competitive advantages of fabless and integrated semiconductor firms.
    • 
      
    • https://www.linkedin.com/in/dylanpatelsa/

 

[blueone]

I understand the "fake it until you make it" business model but I do not care for it. People are misinformed during the fake it period and sometimes they do not make it.

I completely agree. One can be rigorously self-taught in a field, and it really helps to have expert mentors guiding you, but IMO there is no allowable "faking it" period. Z-e-r-o.

 

[lefty]

I think Dave is working full time now but I know he is still part of Hot Chips.

I understand the "fake it until you make it" business model but I do not care for it. People are misinformed during the fake it period and sometimes they do not make it.

As a result Dylan is banned from SemiWiki and I usually delete references to his posts but I let this one stand to see how it goes. Unfortunately:

"Intel has also confidentially stated that they are manufacturing ready for EUV lithography in their Intel 4 process node. We don’t really believe them
because internal documents we obtained show Intel’s first high-volume product utilizing EUV, Meteor Lake, has been delayed yet again, with“ ready-to-ship” dates delayed until Week 52, 2023 at minimum."

The problem here is that, to gain credibility, he referenced internal Intel documents that he should not have, right? Not acceptable at all.

And just to be clear, your Intel sources agree that Intel 4 is not EUV ready? If so you need better Intel sources.

In fairness, he says internal documents say Meteor lake is delayed and assumes that's due to Intel 4. There is also a rumour that Arrow Lake has been delayed.

 

[jms_embedded]

This is a source you trust? You do realize this gentleman has zero semiconductor education or experience.

I understand the "fake it until you make it" business model but I do not care for it. People are misinformed during the fake it period and sometimes they do not make it.

As a result Dylan is banned from SemiWiki and I usually delete references to his posts but I let this one stand to see how it goes. Unfortunately:

"Intel has also confidentially stated that they are manufacturing ready for EUV lithography in their Intel 4 process node. We don’t really believe them
because internal documents we obtained show Intel’s first high-volume product utilizing EUV, Meteor Lake, has been delayed yet again, with“ ready-to-ship” dates delayed until Week 52, 2023 at minimum."

The problem here is that, to gain credibility, he referenced internal Intel documents that he should not have, right? Not acceptable at all.

Hey, it's your site... you have to decide what standards you want to use to allow/deny posts on external articles.

Patel is not a journalist, and he's not an engineering authority. And I don't have any agenda in seeing either more or less of SemiAnalysis material on this site. But I don't think he misrepresents himself, and he brings up some interesting food for thought, which in my mind is just as valid to discuss as other external sources (DigiTimes, TrendForce, etc.) which may have their flaws.

We all have to do our due diligence in deciding how to process media information. I have no doubt that any media publication posted on this site will be called out if there is any misinformation or poor conclusions.

 

[Daniel Nenni]

In fairness, he says internal documents say Meteor lake is delayed and assumes that's due to Intel 4. There is also a rumour that Arrow Lake has been delayed.

He says he has Intel internal documents, does that not bother you? And just because a chip is delayed it doesn't not mean a process is not EUV ready. This is complete nonsense. If Intel is using chiplets the multiple dies will come from multiple processes. The thing about chiplets is putting them all together is a very difficult thing. If I were to bet on the reason for a chip delay it would the integration of chiplets. Chiplets, easy to say but much harder to do.

 

[Maximus]

He says he has Intel internal documents, does that not bother you? And just because a chip is delayed it doesn't not mean a process is not EUV ready. This is complete nonsense. If Intel is using chiplets the multiple dies will come from multiple processes. The thing about chiplets is putting them all together is a very difficult thing. If I were to bet on the reason for a chip delay it would the integration of chiplets. Chiplets, easy to say but much harder to do.

I agree with the logic flaw: Delay of MTL is not equal to delay of Intel 4. There're also other clues indicate that packaging is the yield limiting step of MTL now.
I'm new to this field so I have one question: When packaging yield is not good enough, do people usually make millions of dies first or ramp up dies production after packaging yield reach to an acceptable level?

 

[lefty]

He says he has Intel internal documents, does that not bother you? And just because a chip is delayed it doesn't not mean a process is not EUV ready. This is complete nonsense. If Intel is using chiplets the multiple dies will come from multiple processes. The thing about chiplets is putting them all together is a very difficult thing. If I were to bet on the reason for a chip delay it would the integration of chiplets. Chiplets, easy to say but much harder to do.

Why would it bother me?
Yes, it could be the product itself is having problems. But then again it could be problem with the Intel 4 node. It's not unheard of to have yield problems on a new node.