Intel Foundry Fails To Impress Once Again, 18A Process “Yield Rates’ Are Reported To Be Only 10% Making Mass-Production Impossible FROM wccftech

[hskuo]

News: Rumor?? Truth?​

Intel Foundry Gets Struck With Another "Massive" Problem, Making Division Sell-Off Imminent For Now​

Team Blue is having a hard time finding a breakthrough in the industry since all its divisions are massively underperforming. In particular, Intel Foundry, a part of the firm's "core strategy" for an economic revival, is now witnessing significant barriers to adoption from the markets, mainly due to fierce competition and sluggish performance. In a report by the Korean media outlet Chosun, it is now said that Intel Foundry's high-anticipated 18A process has a yield rate of less than 10%, making it impossible for the semiconductor to reach mass-production stages.

Related Story Intel Apparently Made Former CEO Pat Gelsinger A Scapegoat For Defending Sluggish Business, Claims Channel Partners​

While the report cites a figure that is hard to believe, it might be the "bitter reality" given the recent change in circumstances at Intel. Broadcom, which is said to be a "prime" IFS customer, reportedly wasn't satisfied with Intel's 18A process at all, with their engineers claiming that the process isn't in a position to reach high-volume production. This was associated with lesser "yield rates," although we never did get an actual number before until now. The Korean media outlet claims Broadcom has canceled its orders at Intel and is now looking for viable alternatives.

It is said that the lack of yield rates and the lack of success with IFS were among the primary reasons why Intel's CEO Pat Gelsinger was apparently "fired" from his position. Another catalyst here was due to the under-performing IFS; Team Blue failed to secure larger subsidies from the US government, which acted as the final blow for the termination of Gelsinger. Things aren't looking for Intel Foundry, and a division sell-off looks imminent now.

While Intel is struggling with its current nodes, it seems like arch-rival TSMC is well-settled with its offerings. Despite being slightly behind "node size," TSMC's N2 (2nm) process is said to be far superior to Team Blue's 18A (via Tom's Hardware), mainly due to a higher "SRAM density." This acts as a pivotal factor, given that SRAM density is key in deciding node efficiency and performance, and it looks like TSMC has taken the lead this time as well.

With a key "IFS advocate" now out of the way, Intel might shift its focus away from the foundry business to the manufacturing and product divisions, which could mean that an IFS sell-off or merger deal isn't off the books for now.

Intel Foundry Fails To Impress Once Again, 18A Process "Yield Rates' Are Reported To Be Only 10% Making Mass-Production Impossible

Intel's 18A process, a node that is said to be a "turning point" for Intel Foundry, is now being said to feature only 10% yield rates.

wccftech.com

 

[jorgequinonez]

Does Chosun have a track record for reported accurate information?

 

[Brady]

Their head of Foundry speaking publicly and subject to SEC rules isn’t speaking as if yields are abysmal…

 

[Artificer60]

I have to be somewhat skeptical of a Korean news source that says Samsung has a better process. Not that it is impossible, just that it is hardly an impartial source. And as was pointed out here before, Broadcom didn't cancel their orders, they just said the 18A wasn't ready for HVM.

 

[MKWVentures]

News: Rumor?? Truth?​

Intel Foundry Gets Struck With Another "Massive" Problem, Making Division Sell-Off Imminent For Now​

Team Blue is having a hard time finding a breakthrough in the industry since all its divisions are massively underperforming. In particular, Intel Foundry, a part of the firm's "core strategy" for an economic revival, is now witnessing significant barriers to adoption from the markets, mainly due to fierce competition and sluggish performance. In a report by the Korean media outlet Chosun, it is now said that Intel Foundry's high-anticipated 18A process has a yield rate of less than 10%, making it impossible for the semiconductor to reach mass-production stages.

Related Story Intel Apparently Made Former CEO Pat Gelsinger A Scapegoat For Defending Sluggish Business, Claims Channel Partners​

While the report cites a figure that is hard to believe, it might be the "bitter reality" given the recent change in circumstances at Intel. Broadcom, which is said to be a "prime" IFS customer, reportedly wasn't satisfied with Intel's 18A process at all, with their engineers claiming that the process isn't in a position to reach high-volume production. This was associated with lesser "yield rates," although we never did get an actual number before until now. The Korean media outlet claims Broadcom has canceled its orders at Intel and is now looking for viable alternatives.

It is said that the lack of yield rates and the lack of success with IFS were among the primary reasons why Intel's CEO Pat Gelsinger was apparently "fired" from his position. Another catalyst here was due to the under-performing IFS; Team Blue failed to secure larger subsidies from the US government, which acted as the final blow for the termination of Gelsinger. Things aren't looking for Intel Foundry, and a division sell-off looks imminent now.

While Intel is struggling with its current nodes, it seems like arch-rival TSMC is well-settled with its offerings. Despite being slightly behind "node size," TSMC's N2 (2nm) process is said to be far superior to Team Blue's 18A (via Tom's Hardware), mainly due to a higher "SRAM density." This acts as a pivotal factor, given that SRAM density is key in deciding node efficiency and performance, and it looks like TSMC has taken the lead this time as well.

With a key "IFS advocate" now out of the way, Intel might shift its focus away from the foundry business to the manufacturing and product divisions, which could mean that an IFS sell-off or merger deal isn't off the books for now.

Intel Foundry Fails To Impress Once Again, 18A Process "Yield Rates' Are Reported To Be Only 10% Making Mass-Production Impossible

Intel's 18A process, a node that is said to be a "turning point" for Intel Foundry, is now being said to feature only 10% yield rates.

wccftech.com

18A is not ready for HVM ramp yet??? It shouldnt be. It is still in development.

Now if customer test wafers are not working or matching PDK, that is a bigger issue.

 

[OneEng]

18A is not ready for HVM ramp yet??? It shouldnt be. It is still in development.

Now if customer test wafers are not working or matching PDK, that is a bigger issue.

Shouldn't there be 18A production readiness reports if they plan to produce HVM products in 6 months (according to Intel roadmaps)? Also, I thought I saw Qualcomm was signed up for a 18A HVM part by October.

 

[MKWVentures]

Shouldn't there be 18A production readiness reports if they plan to produce HVM products in 6 months (according to Intel roadmaps)? Also, I thought I saw Qualcomm was signed up for a 18A HVM part by October.

no qualcomm part anytime soon... where did you see that?

The readiness reports shows 50 items that need to be fixed .... just like Naga said. and they are probably at the "we are finding new issues faster than we are solving old ones" due to ramping on new tools.

No production parts will be shipped until 2H 2025 at earliest... which is as expected

 

[dkr1986]

Any mention of Yield of a process should come along with Die size of the chip!. Based on the leaks of Panther Lake tile size of 8mm x 14.288 mm and Pat's statement of D0<0.4 in September, the roughly calculated Yield is 65%. Obviously there is more to it in reality but 10%, that must be a big die!

SemiAnalysis Die Yield Calculator

Experiment with Semiconductor Die Yield, all from the comfort of your browser.

semianalysis.com

 

[Brady]

Reticle limit puts it at sub-10% but no one is doing reticle limit-pushing mega-SoCs on a brand new leading edge node, while it’s still in development. Not even TSMC who pipe cleans with Apple’s smaller A-series SoCs.

 

[hist78]

It's reported that Pat Gelsinger visited Taiwan in early November to talk to TSMC. There must be something very important to Intel that Pat felt he must fly to Taiwan to talk to TSMC in person.

My guesses are:

1. Intel wants to increase the order volume and/or types significantly at TSMC.

2. Intel wants to reduce the order volume and/or types significantly at TSMC.

3. Pat Gelsinger wants to deliver new year best wishes to TSMC in person.


"Intel CEO Pat Gelsinger was recently in Taiwan for a brief visit to meet with TSMC chairman C. C. Wei at the Hsinchu Science Park (HSP), according to sources familiar with the matter."

Intel CEO briefly visits Taiwan to finalize 3/2nm production capacity at TSMC

Intel CEO Pat Gelsinger was recently in Taiwan for a brief visit to meet with TSMC chairman C. C. Wei at the Hsinchu Science Park (HSP), according to sources familiar with the matter.

www.digitimes.com

 

[dkr1986]

It's reported that Pat Gelsinger visited Taiwan in early November to talk to TSMC. There must be something very important to Intel that Pat felt he must fly to Taiwan to talk to TSMC in person.

My guesses are:

1. Intel wants to increase the order volume and/or types significantly at TSMC.

2. Intel wants to reduce the order volume and/or types significantly at TSMC.

3. Pat Gelsinger wants to deliver new year best wishes to TSMC in person.


"Intel CEO Pat Gelsinger was recently in Taiwan for a brief visit to meet with TSMC chairman C. C. Wei at the Hsinchu Science Park (HSP), according to sources familiar with the matter."

Intel CEO briefly visits Taiwan to finalize 3/2nm production capacity at TSMC

Intel CEO Pat Gelsinger was recently in Taiwan for a brief visit to meet with TSMC chairman C. C. Wei at the Hsinchu Science Park (HSP), according to sources familiar with the matter.

www.digitimes.com

We already know that Lunar Lake was initially planned to be niche product at 1/3rd of the current volume planned. It may be related to that change.
They are really going to crank LNL volume up next year per Dave Zinsner during the UBS conference last week (impact on margin due to Memory on Package).

It is possible they are still planning to use TSM for future products as Intel's capacity on Intel 18A will be limited even into 2026.
Compared to what they had in Intel 7 @2023 that is used for ADL/RPL in desktop and laptops and SPR/EMR in DC CPUs even with some overcapacity built during COVID (reason for write off last quarter), the 18A capacity seems low @2026 (will be even lower now with fab delays announced recently). Is this enough for Panther Lake (PTL), Clearwater Forrest (CWF), Diamond Rapids (DMR)??? + External customers.

 

[Daniel Nenni]

It's reported that Pat Gelsinger visited Taiwan in early November to talk to TSMC. There must be something very important to Intel that Pat felt he must fly to Taiwan to talk to TSMC in person.

My guesses are:
1. Intel wants to increase the order volume and/or types significantly at TSMC.
2. Intel wants to reduce the order volume and/or types significantly at TSMC.
3. Pat Gelsinger wants to deliver new year best wishes to TSMC in person.

"Intel CEO Pat Gelsinger was recently in Taiwan for a brief visit to meet with TSMC chairman C. C. Wei at the Hsinchu Science Park (HSP), according to sources familiar with the matter."

Intel CEO briefly visits Taiwan to finalize 3/2nm production capacity at TSMC

Intel CEO Pat Gelsinger was recently in Taiwan for a brief visit to meet with TSMC chairman C. C. Wei at the Hsinchu Science Park (HSP), according to sources familiar with the matter.

www.digitimes.com

I pick #2, renegotiate the contract Bob Swan signed before the Intel BoD fired him.

 

[hist78]

I pick #2, renegotiate the contract Bob Swan signed before the Intel BoD fired him.

Not #3?

 

[Fred Chen]

Obviously D0 is not a steady number, it can go up or down.

 

[Barnsley]

Do Partial die have any use?

 

[Barnsley]

Any mention of Yield of a process should come along with Die size of the chip!. Based on the leaks of Panther Lake tile size of 8mm x 14.288 mm and Pat's statement of D0<0.4 in September, the roughly calculated Yield is 65%. Obviously there is more to it in reality but 10%, that must be a big die!

SemiAnalysis Die Yield Calculator

Experiment with Semiconductor Die Yield, all from the comfort of your browser.

semianalysis.com

View attachment 2539

The defective die is what?

A defect?

Or that particular die didnt resolve correctly during the process?

 

[Barnsley]

Which particular levels are causing the issues?

 

[Xebec]

It's reported that Pat Gelsinger visited Taiwan in early November to talk to TSMC. There must be something very important to Intel that Pat felt he must fly to Taiwan to talk to TSMC in person.

My guesses are:

1. Intel wants to increase the order volume and/or types significantly at TSMC.

2. Intel wants to reduce the order volume and/or types significantly at TSMC.

3. Pat Gelsinger wants to deliver new year best wishes to TSMC in person.

lol @ #3

Less likely, but they also have a few "coopetition" topics such as:

A. Whether or not to encourage ASML and others for certain future tech like HyperNA, wafer changes, etc. (and what kinds of tech)

B. Other supply chain challenges/opportunities that might not warrant enough secrecy to keep to themselves

C. (Intel as a customer) reprioritizing certain wafer allocations for Intel products @ TSMC (i.e. just a change not a net negative or positive)

 

[XYang2023]

PG just posted a twit implying that is a fake news.

x.com

x.com

 

[Mickey]

I pick #2, renegotiate the contract Bob Swan signed before the Intel BoD fired him.

lol @ #3

Less likely, but they also have a few "coopetition" topics such as:

A. Whether or not to encourage ASML and others for certain future tech like HyperNA, wafer changes, etc. (and what kinds of tech)

B. Other supply chain challenges/opportunities that might not warrant enough secrecy to keep to themselves

C. (Intel as a customer) reprioritizing certain wafer allocations for Intel products @ TSMC (i.e. just a change not a net negative or positive)

@Daniel Nenni I second your comment.

Money.udn.com is a credible Economic news source in Taiwan, reported (2024-10-31 01:00 Taipei time)

“TSMC (2330) has seen strong demand for its advanced manufacturing processes. It is reported (private source) that tSMC has expired the original discount of up to 40% of the 3nm process foundry price, and asked Intel to pay the original (current) price instead. This will help TSMC's subsequent profits soon.“

It appears to me that, as anticipated, Pat was unsuccessful in the price negotiation mission, which has further strained Intel’s outsourcing balance sheet shortly after a grace period granted by tSMC (a Quarter or a few months). This seems likely, I can see, to be the final tipping point for the Board of Directors to make a decisive judgment to find a CEO replacement.