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I worked on a product called "Isis" at Racal Redac (now Zuken) back in the 80's which they acquired from Inmos (who had created it because they needed a better tool than they could buy). It performed real-time DRC and electrical connectivity checking using multi-threading on 68K boxes and micro-VAXs. Redac dumped it because they didn't see how it fit in with their PCB business.
So at this point in time I think I would have to see a lot more in a layout tool than RT-DRC to be impressed, particularly since it was a very small team that worked on Isis - not major EDA players collaborating.
Thanks for the perspective on what's been tried before.
To me what's different now compared to the 80's is that we have literally hundreds of rules for IC layout at the 28nm node, while in the 80's it was only a handful of rules.
It's too bad that Racal Redac didn't stick with the IC side of the EDA business, we could use more competition.
The Real Time aspect replaces the highly iterative batch DRC/LVS runs, so it is a real time saver.
One odd point was that Mentor integrated the Calibre RealTime with Laker before their own internal tool IC Station. That tells me something about the market demand for Laker over IC Station.
Generally this is a legacy software problem where companies start off doing "polygon pushing" (aka "dumb") layout tools, and then don't have the ability to re-architect them to include the DRC checks. The number of rules isn't really the issue since any single change usually has limited DRC scope - i.e. DRCing a single change doesn't take that long - the problem is that if the DRC tool is being cranked up on the fly then you have to repeatedly recreate a database or parts of it in the DRC tool to match the layout tool. It's just a lot easier if you design the layout database to support both tasks from the get-go.
At this point I would have expected someone to have come up with a common database for handling both PCB and IC layout (and other stuff like interposers), with sufficient abstraction that you can use the same approach to DRC/ERC across all levels of a design. I was looking at someone's PCB RF analysis tool the other day, and decided that it was of limited value if you don't consider all the components plugged into the board too (and their internal wiring).
Mentor has followed the strategy of integrating with all major layout tools since the early days of the Calibre product line. What is unique about Calibre RealTime is exactly what you’re suggesting, i.e., it is integrated directly to Laker via mechanisms of the Open Access standard, resulting in immediate results without the need to do data streaming between tools. Unlike the </SPAN>Internal</SPAN> DRC </SPAN>checkers </SPAN>used by</SPAN> layout tool</SPAN>s</SPAN>, Calibre RealTime performs sign-off quality checking based on complete foundry qualified decks, and includes</SPAN> advanced rule</SPAN>-</SPAN>based</SPAN> litho checking and other Design-for-Manufacturing (DFM) analyses critical to verifying expected performance at advanced nodes. As we move into double patterning, it will be even more important to get immediate feedback on layout rule violations with hints from the tool on how to resolve them</SPAN> using the sign-off DRC deck</SPAN>.</SPAN> Customers that are using Calibre RealTime have seen this capability result in a 2 week reduction in cycle time, which for them is significant and impressive. </SPAN></SPAN>
Posted on behalf of Joe Davis, Program Manager, Calibre User Interface and Integration:
Double patterning during DRC can be treated in a number of ways. The simplest is to treat is as an arbitrary rule in which the only information given to the designer is the error shape. This is the “just adds rules to the deck” scenario and doesn’t give the designer a lot of useful feedback. However, since double patterning is the application of an algorithm and not just an arbitrary “weak spot” in the process, it is possible to give the designer much more information for debugging. The first piece of information that can be provided is the mask decomposition so that the designer can see which geometries are on opposite masks and make an engineering decision on which geometries to move to fix the problem. However, as with other complex DRC rules, there are many possible solutions for most errors. We can improve the decision process even more by applying Mentor Graphics’ patented algorithm to the error and provide ‘warning rings’. These warning rings tell the designer that if they move a polygon touching this ring, the double patterning error will get bigger, not smaller. Thus, the designer can know what won’t fix the problem, at least. All of these scenarios have to be coded into the deck, but Calibre RealTime supports all scenarios, from the simplest to the most sophisticated.
