There are some interesting points on this one:
Pat: Yeah, and explaining that statement a little, I’m already the #2 foundry in the world. If you count internal wafers. So when I say #2 foundry by 2030, I mean [for our] external foundry [business only]. That is a very substantive statement because we’re saying that we’re going to be, by revenue, the #2 foundry by the end of the decade. That’s the goal that I’ve set out for our team, and that’s above the revenue that I get from the internal foundry business. So it’s a combination from both. I believe it’s going to be a big number by the end of the decade, but we’re trying to be very transparent. I’ll say, appropriately comparable, my external foundry will be #2 in the industry - obviously we expect TSMC to be #1, and by then we’ll have bypassed GlobalFoundries, UMC and Samsung as the #2 revenue foundry in the world.
D.A.N. I did not know this. This is significant. IFS will pass Samsung without internal revenue even though Samsung counts internal revenue? Given that TSMC N3 has all of the design wins and TSMC N2 is expected to be even bigger Samsung maybe easier to beat? Or will Intel remove Samsung internal revenue from the calculation?
Pat: Well, Foveros and CoWoS are pretty comparable. They’re a little bit different. Clearly due to some of the supply limitations that you described, some of our advanced packaging customers today are taking Foveros, and we’re helping them to be able to move their CoWoS designs to Foveros. It’s just taken up by supply chain, and ‘hey, you have advanced packaging capabilities’ - we can do Foveros with you. This gives us more volume of our AI chips, and most of these are AI customers, so this gives us what I call the “fast on-ramp” into the foundry business.
But now that we’re starting to work with them, we can start to explain that CoWoS and Foveros are square functions - you're scaling in both the X and the Y, and that’s a pretty expensive base die. If we use EMIB for the high performance bridged connection, that is way more cost effective in a lot of circumstances [than a single large base die], and the customers are starting to look at our packaging technologies. They’re saying “wow, so I can use some for EMIB and some for Foveros and get a more economic and high performance design, that’s pretty interesting”, and then they’re starting to see some of the advanced testing capabilities that we provide. When you're bringing many of these components together onto an advanced package, all of a sudden the individual die or chiplet, and the testing associated with that, becomes very critical in the overall yield of the cost structure of the full complex advanced package. So we do full performance simulated die test, another differentiated capability. Then we tell them about Foveros Direct - now I can do full die-on-die 3D assembly. So I’m innovating in X,Y and Z dimension, and I’m able to pick which transistors I’m moving to the most advanced node, or which ones like analog or cache cells might be better on a node or two behind - being able to put those together with sub-10 micron bump pitch technology. These are pretty exciting capabilities, so we expect this to be a pretty meaningful on ramp for our overall foundry customers - that not only are we a second supplier, but we become their best supplier.
D.A.N. I mentioned this before, TSMC being packaging limited opens the door for IFS. TSMC refusing to do packaging for non TSMC wafers may be an issue. While they are packaging limited I understand it. But with the chiplet revolution coming on strong TSMC will have to change this TSMC wafer only policy.
The economics of HNA-EUV was also very interesting. There is a lot more, give it a listen and let me know what you think:
Pat: Yeah, and explaining that statement a little, I’m already the #2 foundry in the world. If you count internal wafers. So when I say #2 foundry by 2030, I mean [for our] external foundry [business only]. That is a very substantive statement because we’re saying that we’re going to be, by revenue, the #2 foundry by the end of the decade. That’s the goal that I’ve set out for our team, and that’s above the revenue that I get from the internal foundry business. So it’s a combination from both. I believe it’s going to be a big number by the end of the decade, but we’re trying to be very transparent. I’ll say, appropriately comparable, my external foundry will be #2 in the industry - obviously we expect TSMC to be #1, and by then we’ll have bypassed GlobalFoundries, UMC and Samsung as the #2 revenue foundry in the world.
D.A.N. I did not know this. This is significant. IFS will pass Samsung without internal revenue even though Samsung counts internal revenue? Given that TSMC N3 has all of the design wins and TSMC N2 is expected to be even bigger Samsung maybe easier to beat? Or will Intel remove Samsung internal revenue from the calculation?
Pat: Well, Foveros and CoWoS are pretty comparable. They’re a little bit different. Clearly due to some of the supply limitations that you described, some of our advanced packaging customers today are taking Foveros, and we’re helping them to be able to move their CoWoS designs to Foveros. It’s just taken up by supply chain, and ‘hey, you have advanced packaging capabilities’ - we can do Foveros with you. This gives us more volume of our AI chips, and most of these are AI customers, so this gives us what I call the “fast on-ramp” into the foundry business.
But now that we’re starting to work with them, we can start to explain that CoWoS and Foveros are square functions - you're scaling in both the X and the Y, and that’s a pretty expensive base die. If we use EMIB for the high performance bridged connection, that is way more cost effective in a lot of circumstances [than a single large base die], and the customers are starting to look at our packaging technologies. They’re saying “wow, so I can use some for EMIB and some for Foveros and get a more economic and high performance design, that’s pretty interesting”, and then they’re starting to see some of the advanced testing capabilities that we provide. When you're bringing many of these components together onto an advanced package, all of a sudden the individual die or chiplet, and the testing associated with that, becomes very critical in the overall yield of the cost structure of the full complex advanced package. So we do full performance simulated die test, another differentiated capability. Then we tell them about Foveros Direct - now I can do full die-on-die 3D assembly. So I’m innovating in X,Y and Z dimension, and I’m able to pick which transistors I’m moving to the most advanced node, or which ones like analog or cache cells might be better on a node or two behind - being able to put those together with sub-10 micron bump pitch technology. These are pretty exciting capabilities, so we expect this to be a pretty meaningful on ramp for our overall foundry customers - that not only are we a second supplier, but we become their best supplier.
D.A.N. I mentioned this before, TSMC being packaging limited opens the door for IFS. TSMC refusing to do packaging for non TSMC wafers may be an issue. While they are packaging limited I understand it. But with the chiplet revolution coming on strong TSMC will have to change this TSMC wafer only policy.
The economics of HNA-EUV was also very interesting. There is a lot more, give it a listen and let me know what you think:
. 
Go Intel!