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How are gate counts measured?


Active member
If I have VHDL or Verilog and I use an EDA tool to synthesize a design from this, does it measure # of gates used or # of transistors used or area? If someone mention a design is "1200 gates", what is one "gate" assumed to be? 4 transistors? (for a CMOS NAND gate)
Logic synthesis tools require a cell library, and each cell has an area assigned to it, but the results of synthesis depend on how you control the tool. If you ask for maximum speed, then synthesis may return a higher gate count along the critical paths, trading off more area for higher speed. If you ask for minimum area, then synthesis often trades off a slower clock speed for a smaller area. Each cell in the library also has a gate count number assigned, so that a 2 input NAND gate with 4 transistors is counted as 1 one gate.
Each cell in the library also has a gate count number assigned, so that a 2 input NAND gate with 4 transistors is counted as 1 one gate.

OK so it's the actual number of gates, rather than a 4-transistor NAND equivalent? (so a CMOS NOT gate would be 2 transistors, and an XOR gate would be more than 4 transistors depending on the implementation)

I'm trying to understand the context of statements like this article on RISC-V, and how to understand the conversion between gate count and transistor count:

For example, SiFive recently discussed an implementation of the RV32E that can be configured to be implemented in just 13,500 gates. ZERO-RISCY, a core developed as part of the PULP platform for energy-efficient computing, has a two-stage pipeline implementation that consumes 11,600 gates.

Is gates-per-unit-area a constant for a given fabrication process, e.g. TSMC 28nm LP? If not, why is gate count used as a metric?
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The Inverter, or NOT gate only has 2 transistors, so would count as half a gate. The CMOS XOR gate can have 12 transistors, so would count as 3 gates. Transistor count is quite precise, and not open to interpretation. Some engineers see ICs as collections of transistors, like me, because I was a circuit designer and only simulated transistors in SPICE, while others prefer to use gates, likely because they were logic designers and worked at that level of abstraction and simulated with Verilog using gate primitives. We mostly use Millions of Transistors per square mm to talk about a logic process density, and then separately talk about SRAM bit cell sizes for memory, see this Wikipedia page for an example comparing 7nm process nodes between: Samsung, TSMC, Intel and SMIC.
Assume about 5 or 6 poly-gates per cell, N and P. So if he polygate pitch is 100nm, and the stdcell height is 500nm, then the average logic cell area = 0.5um * 0.6um