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HBM Pin Combinations – Table 2A


Staff member

In previous blog posts, we have discussed the Human Body Model (HBM) waveform and traditional HBM pin combinations. In this post I will discuss the updated pin combinations available in the HBM standard JS-001 2017 and the motivations for those pin combinations. Unless you are familiar with the traditional HBM pin combinations I would suggest that you read the traditional pin combination blog before continuing the current blog.

Issues with Traditional HBM Pin Combinations

The traditional pin combinations, as presented in Table 2B of JS-001 2017, were developed in the 1980s. Even at that time it was recognized that stressing each pin versus every other pin one at a time would create very long test times. To create a more reasonable set of pin combination the traditional pin combinations were developed. The traditional pin combinations are in Table 2B of JS-001 and are reproduced in Table 1 below. In Table 2B each power supply domain was attached to terminal B (ground side) and all other pins were stressed to that pin one at a time. After cycling though all of the power supply domains being connected to the B terminal, each non-supply pin was stressed versus all other supply pins tied together. The traditional pin combinations kept test times to reasonable levels, and they served the industry very well for many years. Over the last 20 years, however, pin counts have continued to increase and, in some ways even more significant, the number of power supply domains have increased dramatically on some high pin count devices.

There are three basic issues with the traditional pin combinations in today’s high pin count devices:
  • - Long test times for devices with large numbers of power supply domains
  • - Repeated stressing of specific protection structures which can lead to wear out
  • - Tests which almost never result in failures


Long Test Times

Consider Figure 1, which presents a simplified representation of an integrated circuit with multiple power domains. Not shown is that the VDD1/VSS1 section of the circuit will have multiple inputs, outputs and bidirectional buffers. Also not shown is that each of the other VDDx/VSSx sections of the circuit are likely to have multiple inputs and outputs as well. Note that VSS and GND busses are considered power domains for HBM testing.

When input I1 is stressed positive versus VSS1 in Figure 1 the current flows through the steering diode to VDD1, down through the VDD1 to VSS1 protection circuit and finally out through the VSS1 line. Stressing input I1 to any of the other VSSx pin groups exercises this same path again, in addition to flowing through the isolation diodes and finely to the VSSx lines. This shows that as power domains, either VDDx or VSSx, are added the required number of HBM stresses increases. For example, if an integrated circuit has 300 IOs and a small power section is added with a single VDDx pin and single VSSx pin, 1200 additional HBM stresses are added to the pin combinations, 300 positive and 300 negative stress to both VDD and VSS.


Repeated Stressing of Protection Elements

As the total number of stresses increases due to additional power domains certain circuit elements get stressed multiple times. For example, in Figure 1 Supply 1 Protection is stressed every time there is a positive stress to any IO powered by VDD1 and VSS1 with respect to VSS1 or to any VSSx or VDDx other than supply region 1. Similarly, the isolation diodes between different VSSx regions will be stressed multiple times for any cross-power supply stresses. These repeated stresses can lead to wear out of these elements as hundreds or even thousands of stresses are applied to the same circuit element.

It is tempting to say that all circuit elements in an ESD path should be able to survive repeated stresses, but this is neither practical or necessary. HBM testing is intended to ensure that an integrated circuit can survive manufacture in an ESD controlled manufacturing facility. Under these conditions an integrated circuit is expected to only experience at most several ESD stresses during its manufacturing process. Testing to survive hundreds or thousands of repeated stresses is not realistic or necessary.

Tests That Seldom Create Failure

The final test called out for in Table 2B of JS-001 2017, see Table 1 requires that each non-supply pin be stressed versus all other non-supply pins tied together. The experience of the members of the HBM working group was that this test very seldom produces failures, and why continue to do a test which never fails? As will be explained in Section 3.2, it is not surprising that this pin combination seldom fails in a way not detected by other pin combinations.

Summary of Tables 2B Issues

In summary, for high pin count integrated circuits with a large number of separate power supply groups the pin combinations resulted in excessive test time and can create wear out of some parts of the ESD protection network due to being stressed hundreds or even thousands of times. Additionally, the non-supply pin to all other non-supply pin tests seldom create failures and is usually not a value-added test.

Updated Pin Combinations in JS-001 2017 Table 2A

There are two fundamental changes in JS-001 Table 2A from the traditional pin combinations in Table 2B and these are shown in Table 2 which shows the edits required to change Table 2B into Table 2A. The first change is that non supply pins are only stressed to power supply groups that are “associated” with the non-supply pin being tested. The second is that each non-supply pin is no longer stressed with respect to all other non-supply pins tied together. The only non-supply to non-supply stressing required is if two non-supply pins are “coupled” with each other. We will discuss these two changes separately.


Non-Supply Pins Only Stressed to Associated Power Pin Groups

The key to understanding why it makes sense to only stress non-supply pins to “associated” power pin groups is understanding how some complex pin combinations are a combination of other less complex pin combinations. For example, see Figure 2 which illustrates how a positive stress from I1 to VDD2 is made up of several simpler pin combinations. The individual stresses are described in Table 3. In fact, there are multiple ways in which the full positive I1 to VDD2 current path is exercised with other pin combinations in Table 2B of JS-001. The full list of possibilities is listed in Table 4.


Table 4 shows that there is considerable redundancy in testing the current path for positive stress of I1 with respect to VDD2. The new pin combinations in JS-001 Table 2A take advantage of this redundancy to reduce stress time and overstress. Table 2 shows that in lines 1 through N the only difference between JS-001 Table 2A from Table 2B is the addition of the phrase “Associated with Supply Pin Group X”.

Non-Supply Pins “associated” with a particular Supply Pin Group are non-supply pins which are powered by the Supply Pin Group in question. For example, in Figure 2, I1 and O1 are “associated” with supply pin groups VDD1 and VSS2, while I2 and O2 are “associated” with supply pin groups VDD2 and VSS2. Eliminating stressing to non-associated power pin groups would mean that I1 would no longer be directly stressed with respect to VDD2 or VSS2. Table 5 reproduces Table 4, but shows which stresses in the I1 to VDD2 current path are no longer specifically stressed with JS-001 Table 2A. The change looks very minimal but gives a large improvement in overall test time and reduction of repeated stressing of a number of elements in the protection design.


It is of course important to ask if the elimination of the stressing to non-associated supply pin groups opens up a high probability of missing weakness in the ESD design. Experience of the HBM working group is that HBM failures for stresses such as I1 to VDD2 were invariably also found in a stress from I1 to VSS1 or in stress of VDD1 to VDD2. This makes physical sense.

ESD design weaknesses fall into two categories, weakness in the intended ESD current path, or layout issues creating a current path outside of the intended ESD current path. Let’s consider the I1 to VDD2 example from Figure 2. If there is a weakness in the intended current path that weakness should be seen in one or more of the pin combinations which make up the I1 to VDD2 current path. Table 5 shows that the elements of the I1 to VDD2 path are still stressed multiple times even with the elimination of stress to non-associated power pin groups.

The other possible failure mode is that there is a specific weakness in the design or layout at input I1. If that is the case it is very unlikely that the only pin combination that will see it is I1 to VDD2, since VDD2 is likely in an entirely different region of the integrated circuit. In fact, the most likely stresses to find a weakness in the I1 design are stresses to its associated power groups, VDD1 and VSS1. This matched the experience of the HBM working group when it developed JS-001 Table 2A.

Non-Supply to Non-Supply Stress

The traditional pin combinations, JS-001 Table 2B, required each non-supply pin to be stressed to all other non-supply pins tied together. This was sometimes called the “pin to the world” test. Experience of the working group was that this pin combination essentially never produced failures, or at least never produced failures not seen when stressing non-supply pins versus supply pin groups. This is not a surprising outcome if the expected current paths are examined, as shown in Figure 3.


Figure 3 shows the current paths for a positive stress of I1 versus all other non-supply pins. The current begins with a well-defined path, through the steering diode to VDD1 and then through Supply 1 Protection to VSS1. The current then begins to spread out. The current can flow to all other non-supply pins connected to the power domain VDD1-VSS1 such as O1 as well as all non-supply pins on all other power domains. The only path which sees the full stress current is between I1 and VSS1, which is already stressed separately.

There was therefore considerable sentiment to eliminate all non-supply pin to non-supply pin testing. This was not done because it is known that some “coupled” non-supply pins could be weak when stressed versus each other. The JS-001 definition for a coupled non-supply pin pair is as follows:

Two pins, such as differential amplifier inputs, or low-voltage differential signaling (LVDS) pins, that have between them an intended direct current path, such as a pass gate or resistor.

Based on this the HBM working group replaced the more general non-supply to non-supply stress with stress only between coupled pairs of non-supply pins. This reduces the amount of non-supply to non-supply stressing considerably and focuses on pin combination that could be weak.


The use of the new pin combinations in JS-001 Table 2A considerably reduces test time and excessive stress for high pin count integrated circuits which have a high number of power supply groups. It is important to note that both Table 2A and Table 2B are acceptable for use in HBM testing. Which pin combination to use for HBM testing of a specific integrated circuit is a mix of engineering judgement and a business decision. I will discuss this in an upcoming blog post.

Source: SRF Technologies - Post

Link to Press Release