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Gelsinger Opens Up, as Intel Reportedly Expands Orders to TSMC

I don't think we're disagreeing here... ;-)

One problem is that "PPA" is too simplistic -- if one process is better on all three counts (power *and* performance *and* area) than another then it's obviously "the best", but that's not the issue here -- it's not even the case with the different options within one process, for example comparing the different N3 FlexFin libraries (3-fin, hybrid 3/2 fin, 2 fin, hybrid 2/1 fin, 1-fin) they all have different power/area vs. frequency curves, and are different at different voltages.

Even your last point isn't strictly true -- yes if Intel can get a core to 3GHz with less power than TSMC then that's a winner, but what if the cost is bigger die area so you can't fit as many cores on a chip or the cost is higher (and maybe yield is lower)? It all depends what your priorities are... ;-)

(also GPUs are generally power-limited so don't push clock rates anywhere near CPU ones, it's more efficient to run slower and at a lower non-boosted voltage)

Backside power is another example of this, which Intel are promoting as "the bees' knees" because it helps keep clock rate up, especially at higher supply voltages like CPUs use on boost settings. But the gains at lower clock rates and voltages are a lot smaller (yes I've looked at this in detail), and there's a cost premium to BSP as well as some risk until it's all been pushed out into mass production successfully. From what I've seen it might well be appropriate for Intel and their product mix, but it's less obviously the best choice for TSMC even at N2 for many (most?) customers -- which is presumably why they're introducing it as a second (optional) N2 step a year or so later.

Intel are coming into this battle from a single-customer x86 CPU-centric viewpoint, TSMC are coming from a widely-spread customer base in many areas with CPUs -- x86 or others -- only being a relatively small part of their business. Since the current view is that the massive expansion in ICs over the next few years will be AI-driven not x86-driven, I think Intel are going to have a hard time muscling in on TSMCs market dominance -- but good luck to them for trying, a monopoly is rarely a good thing.
 
Scott has many customers and a long history. His models are not projections. It is not just public information. He has a massive feedback loop with customers and colleagues. If one of his models is wrong he will find out very quickly and make the appropriate tweaks. It may not be perfect but they are the best in the industry.

It will be interesting to see what TSMC says at their upcoming Tech Symposium. The only way to judge Performance, Area, and Power is to run the PDKS with your design. Customers do this so they can make an informed foundry decision. These numbers are not published but customers do share them with TSMC and other ecosystem partners so TSMC cannot make grandiose claims with hundreds of PDKs in customer's hands.

I also call BS on the 5N4Y thing. We all know that Intel 4 and 3 are half nodes. Same as Intel 20A and 18A. So, it should be 3N4Y which is quite an accomplishment considering it took 5 years to do one node (Intel10/7). Nobody trusts Samsung which is why Intel has a great opportunity but people must trust them. And I'm talking about the foundry teams at the top customers, not people sitting on the sidelines.
The whole 5N4Y thing is baffling. We'd all be impressed by 3N4Y. So why devalue the achievement by making such a deliberate overstatement ? It just needlessly puts our backs up and makes us sceptical.

There still seems to be some part of the Intel DNA that can't resist trying to play by different rules to everyone else (like the branding of every new technology they come up with as though it's unique to Intel). Surely the Intel foundry operation needs to break this habit ?
 
The only reason Intel has enough EUV is because they use TSMC's EUV for the majority of the chiplets Intel designs. If not for TSMC where would Intel be? Behind AMD that is for sure.

You are wrong about Scott as well. Since you do not know him I will let it pass.

Are you also saying that Intel only wanted/needed a small fraction of EUV tools sold in FY ‘23?

Will Intel only want a similarly low fraction of EUV tools in FY ’24?
 
Videocardz has a translated leak on Arrow Lake from a few days ago.

The leak claims that the higher end Arrow Lake CPU tile/chiplet will be 20A (6+8 die) and all models below will be TSMC N3. Basically think equivalent i5-K and above, with mid range i5’s maybe on 20A or N3, but anything below definitely on N3.
 
Videocardz has a translated leak on Arrow Lake from a few days ago.

The leak claims that the higher end Arrow Lake CPU tile/chiplet will be 20A (6+8 die) and all models below will be TSMC N3. Basically think equivalent i5-K and above, with mid range i5’s maybe on 20A or N3, but anything below definitely on N3.
@Xebec @fansink @nghanayem

This leak is similar to what we have heard (some sku 20A some TSMC). It is a little more controversial depending on what skus ramp using TSMC CPU and whether they are desktop or mobile. And whether an 20A Arrow lake sku launches in December as committed.... Now we know why TSMC says 20A and N3 are similar in performance.

We will show details in our model for forecasted wafer loadings through 2026 now that Intel has made it public, but I think people should be prepared for the question/paradox of "how many wafers do you have to make per week to claim process leadership?" . We will publish details end of March

Chiplets and Intel's parallel sourcing plans are certainly making this interesting and complex.
 
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