Yes. That detail was also leaked by Moore's law is dead.
Gelsinger Opens Up, as Intel Reportedly Expands Orders to TSMC
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It’s doubtful you have knowledge of TSMC/ASML contracts (or any ASML contracts), which may have been established long before Intel “required” EUV tools. For instance, in 2021 Intel was only purchasing ~5% of ASML’s EUV tool production, while TSMC purchased ~67%, and in 2023, Intel acquired only ~18% vs TSMC’s ~53%.
TSMC may have a long-term contract that allows for a much greater share of ASML’s EUV tools.
I suspect that in 2024, out of the ~67 tools delivered by ASML, TSMC will have >30 vs Intel’s <15.
Scotten Jones is probably the only person to speak intelligently about EUV tool allocation.
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Scotten Jones relevant EUV tool allocation article - https://semiwiki.com/semiconductor-manufacturers/intel/311036-intel-and-the-euv-shortage/
Correct, I have no knowledge of anybody's contracts. But that doesn't change the fundamental reality that when it comes to N2 HVM TSMC has 0 steppers. Their "EUV advantage" doesn't mean anything from the perspective of TSMC's N2 capacity, because with every new node TSMC needs a new fab. A new fab means starting from zero everytime.
Exactly. Intel didn't buy tools they didn't need. Now they do so they are in line with everyone else (and that includes TSMC).
Doubtful, ASML only cares about selling more tools not picking winners and losers. If they starve out the memory manufactures and intel/samsung logic they gives TSMC too much buying power. Given their constant backlog and how TSMC already dominated it, ASML had/has no reason to give TSMC special access. That would only be to the benefit TSMC.
And? As an example let's take last year. Scotten projected that intel would have bought around 20 steppers. The only site that was fitting out last year was Fab34. That hardly sounds like intel is EUV constrained. TSMC for its part bought like 40 per those same projections. TSMC is doing EUV double patterning, intel isn't, and TSMC was fitting out Fab18 P4-6. Even if we assume that 100% of the 2022 projected orders were for N3 fabs, that is 80 total steppers spread over 3 fabs in what will likely be TSMC largest node in corporate history for the next long time so the numbers line up with their capacity needs.
Agreed, however he isn't omniscient. He can misestimate things. That just comes with the territory. For example see his recent environmental analysis. Techinsight's environmental simulations line up very well with real environmental data provided to the various governments. However for intel Oregon, the numbers were off due to underestimating just how much manufacturing happened there.
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Looks like we’ll have to wait for a knowledge-based opinion from the likes of Scotten Jones.
He leaked it? It is common knowledge. What exactly did he leak?
The only reason Intel has enough EUV is because they use TSMC's EUV for the majority of the chiplets Intel designs. If not for TSMC where would Intel be? Behind AMD that is for sure.
You are wrong about Scott as well. Since you do not know him I will let it pass.
He said Arrow Lake CPU tile would use N3B.
What do you mean by that? I think he is an awesome resource. All I said was that there are limits to how accurate techinsights projections can be since they don’t have access to everyone’s books. All things considered their models are really freaking good for only using publicly sourced data and sharp engineering analysis. An example of what I mean was the electricity models for Oregon, which they said they corrected to match their model and other fabs in industry. For other sites their model was right on.
Another was the 18A vs N2 thing. Intel and Techinsights say 18A leads on performance. TSMC says they lead. Who ends up being right, time will tell. What I can say for a fact is TSMC knows better than anyone else how N2 will perform and intel knows 18A better than anyone else. Everything else is an exercise in reverse engineering and good judgment.
Ah, okay. He asks me questions from time to time. Leakers leak a lot of things and sometimes they are right and sometimes they are wrong but we mostly talk about the right ones. Why do you think N3B is not on the TSMC slide? Is there an N3A and N3C?
Maybe, it's a mistake?
N3B stands Base N3 node, N3E is Enhanced N3 node: https://fuse.wikichip.org/news/7375/tsmc-n3-and-challenges-ahead/
Scott has many customers and a long history. His models are not projections. It is not just public information. He has a massive feedback loop with customers and colleagues. If one of his models is wrong he will find out very quickly and make the appropriate tweaks. It may not be perfect but they are the best in the industry.
It will be interesting to see what TSMC says at their upcoming Tech Symposium. The only way to judge Performance, Area, and Power is to run the PDKS with your design. Customers do this so they can make an informed foundry decision. These numbers are not published but customers do share them with TSMC and other ecosystem partners so TSMC cannot make grandiose claims with hundreds of PDKs in customer's hands.
I also call BS on the 5N4Y thing. We all know that Intel 4 and 3 are half nodes. Same as Intel 20A and 18A. So, it should be 3N4Y which is quite an accomplishment considering it took 5 years to do one node (Intel10/7). Nobody trusts Samsung which is why Intel has a great opportunity but people must trust them. And I'm talking about the foundry teams at the top customers, not people sitting on the sidelines.
Why are you linking to Wikifuse? Does David Schor work for TSMC? Show me a TSMC slide with N3B on it.
Just a minor comment here — Intel was the leader in “converting R&D to manufacturing” for decades before TSMC took the lead. It’s entirely possible that with “new old stock leadership” Pat could turn the tables here through his renewed focus on engineering culture @ Intel.
(That said I think it would take several miracles for Samsung to overtake TSMC and Intel..
).Agreed, the quality of the models is second to none in breadth and depth. I guess a better way to phrase "public info", is he literally doesn't get to see the data off of the respective development lines. I have no doubt that they hear plenty of things at the various conferences or access to NDA only parts of OIP, SAFE, or Direct connect to inform or adjust their models. To say nothing of the years of industry experience on many of the folks there.
As I have noted before it is a game of he said she said. And no matter what process is "better" you sure as hell aren't going to be hearing it from the "loser". So at this point I don't really care what CC or Pat have to say on the matter since I already know more or less what they will say. The only thing that is clear is that 18A leads N3P PPA by some amount otherwise TSMC would have used stronger language than "comparable" like they did with N2. As for what TSMC wants to call a "significant lead" your guess is as good as mine. Is at a 5% lead "comparable"? What about 10% or 15%? No clue. And intel for their part only ever talked about wanting to lead in performance per watt, which of course leaves out the AC part of PPAC. But given how far behind intel was, focusing on one thing to do really well is probably a good idea. Doubly so when it is in line with intel's core competency (bringing new transistor archs to HVM).
Agreed, I doubt N2 is a dud on power performance or unconstrained operation.
That was a battle that was lost over a decade ago. This is the nomenclature the whole foundry industry has chosen. For what it is worth I think that the convention has some merit, since N4P-HPC or N4-RF is a whole different beast from N5 even if the base technology is the same. In a world where these nodes get major updates, I think the R&D effort done at the HVM fabs to extend these nodes deserves some level of recognition. Fortunately intel doesn't have the audacity to claim that 10/7, 4/3, and 20/18 are different "full" nodes, so at least there's that.
By this logic it should be 2 nodes in 3 years since 10nm was already in HVM before Ann/Pat struck the 5N4Y stake into the ground in late 2021. The main impressive thing by my book is following up intel 4 with a new node with two major innovations a year later. Of course there is also the obvious intel giving a process roadmap and sticking to it after having 3 nodes in a row that were late.
At this point, Intel has only Fab 34 running these nodes for its customers? https://en.wikipedia.org/wiki/List_of_Intel_manufacturing_sites
The argument about who is right about whether 18A or N3P is better misses the point, which is that there's not always a single "better", depending on the process priorities.
Historically Intel have valued performance (clock rate) over everything else (density, power consumption, yield...) because as an IDM that's what they needed to win in x86 CPUs, TSMC valued other things (density, power consumption, yield...) over clock rate because as a foundry that's what the majority of their customers value most.
Looking at the numbers for 18A and N3P this trend is still there (18A is higher speed but lower density -- as for yield, nobody beats TSMC...) so it's possible they could *both* be right -- 18A is better for Intel CPUs, N3P is better for foundry products, including the fastest-growing volume ones like AI.
Also bear in mind that clocking faster is of little use in many cases if this disproportionately increases power consumption, because gate density is rising a lot faster than power per gate*MHz is falling so power density is continually increasing, which is why many large devices run at lower clock rates than 5GHz headline CPUs -- and even these for HPC applications where all cores run flat out all the time run considerably slower than headline 5GHz clock rates.
All of which favours the TSMC approach over Intel for most applications...
Historically Intel have valued performance (clock rate) over everything else (density, power consumption, yield...) because as an IDM that's what they needed to win in x86 CPUs, TSMC valued other things (density, power consumption, yield...) over clock rate because as a foundry that's what the majority of their customers value most.
Looking at the numbers for 18A and N3P this trend is still there (18A is higher speed but lower density -- as for yield, nobody beats TSMC...) so it's possible they could *both* be right -- 18A is better for Intel CPUs, N3P is better for foundry products, including the fastest-growing volume ones like AI.
Also bear in mind that clocking faster is of little use in many cases if this disproportionately increases power consumption, because gate density is rising a lot faster than power per gate*MHz is falling so power density is continually increasing, which is why many large devices run at lower clock rates than 5GHz headline CPUs -- and even these for HPC applications where all cores run flat out all the time run considerably slower than headline 5GHz clock rates.
All of which favours the TSMC approach over Intel for most applications...
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I guess they don't refer to it as N3B, but everyone else seems to call it that
Not anyone actually using TSMC as opposed to just talking about them... ;-)
We are definitely off topic now
Totally agree. There was a reason I put "better" and "loser" in "" marks. A 130nm bipolar is "better" than both nodes when it comes to the gain from analog at minimum device length. GaN or SiC will beat the socks off these nodes for high voltage applications. As for what TSMC considers "better" for leading edge processes, they said that "N3P is comparable in PPA to 18A". In my experience anyone who tells you their product is "comparable" has a worse product and will then follow up with "...and my product is cheaper". Funnily enough TSMC did the exact same thing and talks about how the more simple process makes them believe that N3P is cheaper than 18A and that it will obviously be more mature in 2025 than 18A will be in 2025. If the PPA of N3P was even 1% better than 18A, I would assume TSMC would have said "better" and not "comparable". As for N2 TSMC said it is "more advanced" and I think they have also claimed that they think it will be better at every metric.
So my read is tacit agreement from TSMC and techinisghts that 18A leads on PPA vs N3P (just from eyeballing that plot that Scotten posted a while ago). Intel says better power-performance than N2, Techinishgts says better performance per watt, and TSMC says complete victory across the board. Time will tell who's reverse engineering assessments will turn out right or wrong.
That was an argument that I made at the time, that technically nothing Pat and CC claim conflict. Highest power-performance and best PPA are not the same thing. Funnily enough I actually think there needs to be a distinction for intel CPUs. Laptop and desktop have these large 1C and all core boost clocks with desktop sustaining said boost clocks for infinite time if you've got the cooling. Their server chips care more about the base freq and lowering per core power to fit more cores into the power budget. A transistor for one isn't necessarily good for the other. I'm sure things were easier in the old days when intel's process lead was so big they could keep the freq lower to maximize PPW.
It depends on what "power-performance" leadership looks like and how AC looks, since the density without looking at areal cost is kind of missing the forest for the trees. If said leadership is hey we use less power at 5GHz, I agree thank you no thank you I'll take my business somewhere else. If it is hey intel can get your GPU/ARM server CPU to 3GHz with less power than TSMC, then we've got a party.
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