[content] => 
    [params] => Array
            [0] => /forum/index.php?threads/gdsii-to-mask-fracturing-flow.13806/

    [addOns] => Array
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2020470
            [XFI] => 1040170

    [wordpress] => /var/www/html

GDSII to Mask fracturing flow


New member
Dear Engineers,

I am curious to the MDP flow that leads to the Mask set once we throw the GDSII over the fence and party over yet another successful tape out and provide DRC waivers to the fab.

Any pointers to docs on EDA tools and how they stitch together in a flow. Over the years seen a lot of presentations eluding to that side of the game but ...

Appreciate your help!

Tom Dillinger


The generation of mask data from the GDSII/OASIS tapeout database has a long history of innovation. To best understand how this flow has evolved, I might suggest using the following chronology of terms in your searches:

(1) "pattern generation" mask tools, e-beam mask writers

PG machines accepted the tapeout data, fractured the shapes into optimal subsets (common sizes/orientations) and "flashed" an exposure onto a high emulsion-coated mask plate. This technology introduced fracturing, but was eventually replaced by e-beam mask writing technology, which remains the norm today. Search for the "MEBES" data format for more info on e-beam mask writing.

(2) optical proximity correction (OPC) algorithms and EDA tools

As dimensions scaled in successive process nodes, the fidelity of rectangular corners on the printed wafer diminished (with the exposing wavelength used at that time). New mask data processing tools were developed to introduce OPC corrections to the design data. Serifs (aka "dogbones") were added to external corners, as an example. Search for "OPC tools", and you'll find a wealth of info.

(3) SRAF, phase attenuation

With successive scaling, the fidelity of individual lines/spaces became an increasing issue, due to diffraction through the opaque and transparent areas on the (chrome) mask. Mask data processing algorithms were enhanced to add "sub-resolution assist features" to provide constructive and destructive interference light intensity adjacent to the design data. Mask manufacturers also pursued alternative techniques for manipulating the interfering phases of transmitted light exposure arriving at the wafer surface. Search for "SRAF" and "alternating phase shift attentuation" to see examples of the types of data modifications that were applied.

(4) SMO, with ILT

The most complex advancement of mask data processing enabled the exposure of advanced line pitches using 193i lithography. Mask exposure equipment was enhanced to provide a spatial light intensity that varied over the field, a significant change from the "uniform exposure intensity" goals of previous generations of mask aligners. The mask shop now had the option of concurrently optimizing the light "source" and "mask" pattern data (SMO), using complex "Inverse Lithography" transformation algorithms optimization algorithms. In short, given the desired exposure pattern + light intensity at the wafer, SMO-ILT derives the mask data and exposure pattern. Search for SMO (and be prepared to dust off your "Optics" textbook from school).

When SMO-ILT was first being introduced, there was a concern that the layout design rules in the PDK "might" enable a DRC-correct pattern that would have difficulty in the mask shop deriving a solution. In addition to running DRC, designers were asked to run an additional step prior to tapeout, to improve the confidence in success with SMO-ILT. Search for "litho process checking" or "litho compliance checking" to learn more about the additional criteria that were used. (These tools typically used a combination of pattern matching techniques to see if your layout contained "high risk" patterns, or perhaps even exercised a detailed SMO-ILT model simulation on a suspected "hotspot" in your layout.)

Your note mentioned "DRC waivers" -- you are actually asking the mask shop to run a litho process check on the area where you are requesting a waiver, to confirm they feel it will print with sufficient exposure margin.

Now, at the same time that these mask data optimizations were being introduced, the design rules in the PDK were getting more restrictive, to alleviate some of the exposure fidelity concerns. Parallel run length-dependent spacing rules were introduced for long wires. "Wrong-way" segments on a metal layer required greater segment width and spacing to adjacent wires. And, ultimately, "all wires must be unidirectional" on specific layers (device gates, too) -- no wrong-way segments allowed at all. And, there were simply some pitches that could not be successfully printed, resulting in "forbidden pitch" design rules.

All of the technologies mentioned above relate to mask exposure using transmitted light energy. With the introduction of EUV lithography, reflective masks are used -- the data corrections applied by the mask shop become even more elaborate, due to the "pattern shift" associated with the incident angle of the EUV light.




New member
Thanks Chipguy,

I really appreciate your response. I most of this stuff like SMO, ILT, and other RET optimizations, by now has been incorporated in EDA tools. Or are they still the "secret sauce" of the fabs.

IMHO, if I can hazard a guess, I suppose till about 45nm its all lingua franca in the EDA tools. And 28nm onwards its all state secret IP. True?

Thanks in advance!