Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/first-high-na-euv-to-arrive-early-for-tsmc.20949/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021370
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

First high-NA EUV to arrive early for TSMC

Daniel Nenni

Admin
Staff member



The Taiwan Semiconductor Manufacturing Company (TSMC) is set to receive its first high NA EUV chip manufacturing machine from the Dutch firm ASML later this month, according to rumors swirling in Taiwan. High NA machines have been a source of controversy when it comes to TSMC, as after its management complained earlier this year that the equipment was pricey, it later decided to buy a scanner from ASML.

These machines use different lenses than their EUV predecessors and enable crisper resolution of smaller circuits, which helps chip manufacturers make advanced and leading edge semiconductors. According to the details, TSMC's high NA EUV scanner costs more than €400 million and might require traffic planning to transport it to the firm's facilities.

TSMC, ASML Refuse To Comment On Whether High NA EUV Scanner Is Arriving In Taiwan This Month​

Taiwanese industry sources believe that after TSMC receives its first high NA EUV scanner later this month, the firm will maintain its edge over its primary contract chip manufacturing rival, Samsung. TSMC and Samsung are the only two firms in the world that manufacture leading edge semiconductors through this business model, and the Taiwanese firm holds a commanding market share due to its strong industry partnerships and consistent product yields.

The sources outlined that TSMC's high NA EUV machine purportedly cost the fab more than €200 million. Its dimensions also create headaches, as the scanner cannot be disassembled in some facilities because some components are taller than the rooms in TSMC's facilities. They added that when the high NA scanner does arrive in Taiwan, it is likely to be transported to TSMC's facilities at night to avoid traffic jams and the potential implementation of special route management plans.

Intel-TSMC.webp

High-NA EUV Lithography Machine from ASML

Additionally, TSMC is also expected to move the machine into its research and development facilities to help with the development of advanced process technologies. The firm's previous comments regarding high NA EUV have seen it assert that the machines might not be needed for several years as current generation EUV scanners are capable of making chips until at least 2026. By then, TSMC plans to manufacture its A16 process technology, which is equivalent to 1.6 nanometers in simple terms.
ASML and TSMC refused to share any details about the scanner purportedly arriving in Taiwan later this month. Intel, which is currently struggling with high costs, took the lead with the high NA equipment by receiving the first machine late last year and firing it up for the first time earlier this year. The firm added in April that it plans to put the machines in production next year in a high stakes move to regain process leadership.

TSMC's primary contract chip manufacturing rival, Samsung, is rumored to receive the first high NA EUV scanner in either Q4 2024 or in 2025. While high NA EUV machines present their unique set of problems, such as requiring chip manufacturers to 'stitch' together half fields, they also improve productivity and throughput. Procuring them far ahead in time enables chip manufacturers to solve the technological complexities before risking mass production or finalizing production timelines with the equipment.

 
This report is "derived" from a Digitimes story that is behind a paywall. So that is really what WaferTech, Tom's Hardware etc... does for a living. Help us avoid paying for content by munging other people's hard work . :ROFLMAO:

 
It takes a couple of years for TSMC to find out the most economical entry point in HVM for their leading customers (like Apple, NVIDIA...) to introduce new machines. I think ASML is now doing all they can to make their top-customer happy and let them experiment with high-NA, the earlier the better. TSMC has been really quite critical about the (list)price of the high-NA machine. As ASML has built up quite some inventory I think, and is struggling with receiving enough orders (some ASML suppliers have been rumored to have low orders from ASML) and is pushing for cost-savings with suppliers and internally, it is clear they have to keep their most important customer happy!
 
It takes a couple of years for TSMC to find out the most economical entry point in HVM for their leading customers (like Apple, NVIDIA...) to introduce new machines. I think ASML is now doing all they can to make their top-customer happy and let them experiment with high-NA, the earlier the better. TSMC has been really quite critical about the (list)price of the high-NA machine. As ASML has built up quite some inventory I think, and is struggling with receiving enough orders (some ASML suppliers have been rumored to have low orders from ASML) and is pushing for cost-savings with suppliers and internally, it is clear they have to keep their most important customer happy!

TSMC has to keep all customers happy and that is a huge amount of wafers that have to go through HNA-EUV. This is real life not a lab experiment. The technology needs to be ready for TSMC style HVM and must offer better PPAC (Power, Performance, Area and Cost). That is the semiconductor way.
 
TSMC has to keep all customers happy and that is a huge amount of wafers that have to go through HNA-EUV. This is real life not a lab experiment. The technology needs to be ready for TSMC style HVM and must offer better PPAC (Power, Performance, Area and Cost). That is the semiconductor way.
And a better price from ASML as well.....no reason for TSMC to have ASML's gross margins to exceed those of TSMC....;)
 
Perhaps TSMC would like to push the development of the hyper NA-EUV machine with throughput of 400 wafers/hour, and totally skip the high-NA EUV version that Intel has ordered some 6-8 tools or so?

At some point the newest low NA-EUV will become so modular and similar in dimensions like the proposed new hyper-NA tool. If ASML can get that done in 2030, perhaps TSMC can insert it after using low-NA EUV from 2019-2030.....?

See roadmap of Martin vd Brink as presented at IMEC 2024:
https://cdn.mos.cms.futurecdn.net/9Q2T4qMEj2WdsMUXfpCjqQ.jpg

Image from the story: https://www.tomshardware.com/pc-com...s-hyper-na-tools-and-radical-euv-speed-boosts
 
Back
Top