Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/fake-news-tsmcs-3nm-foundry-price-breaks-through-20-000-iphone-15-gpu-price-increase.17097/page-2
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021370
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

FAKE NEWS: TSMC's 3nm foundry price breaks through $20,000, iPhone 15, GPU price increase

As for high priority lots, that is a thing, and all fabs have them (as far as I know). However they are very disruptive to the fabs output/hurts wafer cost for the normal lots. For this reason foundries often charge extra for expedited lots. As far as I know development fabs do not have any special setup for high priority lots, just a higher volume of them. Depending on how much new equipment there is for that process impacts how negatively they effect factory output. When it is mostly new tools, then the priority lots don’t have to share with product lots, and cause minimal disruptions. Priority lots for prototypes, items of unexpectedly high demand that a customer is paying extra to expedite, or a new process that is using a large amount of current equipment has a larger impact on output.
How low does the start to finish delay go with priority? That would be some indication of the theoretical opportunity to improve the experience. It might not even be an improvement for everyone. Just doubling the capacity for high priority runs would likely make a lot of engineers happier.

Does dual patterning cost much time? I would assume they could do this as fast as processing a FOUP, then swapping pattern mask, then processing that FOUP again before moving it to be fixed and developed, so the increased mask count in this case does not count as increased process layers or much increase in processing time.
 
How low does the start to finish delay go with priority? That would be some indication of the theoretical opportunity to improve the experience. It might not even be an improvement for everyone. Just doubling the capacity for high priority runs would likely make a lot of engineers happier.
If I told you I'd have to kill you :cool:. Just know that it can be alot faster if the system isn't clogged up with tons of high priority lots, and only moderately faster if there are tons of lots in the fab that are "high priority".

EDIT: I think you misunderstand there isn't dedicated capacity for high priority lots, rather they get to "cut in line" allowing them to spend less time waiting for a load port on the tool to open up (think of it as a Disneyland/world fastpass). Just like a Disneyland/world the fastpass line depends on the number of fastpass holders. Regardless of priority all lots still have to wait for things like wafer handling robots, other wafers in their lot to finish at the current operation, outgassing, ect.
Does dual patterning cost much time? I would assume they could do this as fast as processing a FOUP, then swapping pattern mask, then processing that FOUP again before moving it to be fixed and developed, so the increased mask count in this case does not count as increased process layers or much increase in processing time.
I am outside my wheelhouse here (if I mess up Fred Chen knows what to do ;)), but it depends on the exact dual patterning technique that is used. Some methods require etch and ash steps between exposures. Others have multiple exposures back to back.
 
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EDIT: I think you misunderstand there isn't dedicated capacity for high priority lots, rather they get to "cut in line" allowing them to spend less time waiting for a load port on the tool to open up (think of it as a Disneyland/world fastpass). Just like a Disneyland/world the fastpass line depends on the number of fastpass holders. Regardless of priority all lots still have to wait for things like wafer handling robots, other wafers in their lot to finish at the current operation, outgassing, ect.
I've worked on large scale scheduling algorithms. I was aware you were saying there was no dedicated capacity for priority. But my intuition is that there will be certain bottlenecks which would be the pain points if you, say, doubled the number of priority customers in the system and so there would be some targetted CAPEX on machinery to release those choke points in order to allow more priority work. The priority customers will not be all over the map, they will be concentrated in processes which can deliver high value new products. A few machines - say ashers, or CMP - will show up as their pain points for latency, even if the fab is overall in balance for capacity.
 
Kasprowicz states:
Typical design is 11-Metal process with 66 masks
• @80% fab utilization mfg cost ~$4800 / 300mm wafer
• @ 1.3 layers / day, cycle time is ~90 days (min 3 months from start to delivery)

<I think that last calculation is upside down, should be 50 days start to delivery?>

Given that the FOUP carries 25 wafers which should take less than 10 minutes for all to pass through a litho machine, why does it take 18 hours per layer? Spin on resist is fast. Baking resist is a few minutes. Developing takes minutes. Etching and vapor or vacuum deposition should be minutes. Are any fabs organized for rapid turnaround, for example to build prototypes and pilots where hundreds of people may be idle until they can begin test and verification on the real thing? I'm aware that fabs are fabulous big scheduling problems but would be surprised to discover vast yards where FOUPs hang around doing nothing for hours...

What are the pain points for process latency? It is not the EUV machines...
~1 layer/day is not unreasonable, some tools are not running at advertised WPH, and any maintenance downtime easily leads to hours of idling. Any critical metrology may also add substantial time between actual processing steps, but it would be necessary to get the information to dial in the next step's recipe.

1 layer without metrology being something like: film stack depo => coat/bake => litho => bake => develop => etch => strip/clean
 
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If I told you I'd have to kill you :cool:. Just know that it can be alot faster if the system isn't clogged up with tons of high priority lots, and only moderately faster if there are tons of lots in the fab that are "high priority".

EDIT: I think you misunderstand there isn't dedicated capacity for high priority lots, rather they get to "cut in line" allowing them to spend less time waiting for a load port on the tool to open up (think of it as a Disneyland/world fastpass). Just like a Disneyland/world the fastpass line depends on the number of fastpass holders. Regardless of priority all lots still have to wait for things like wafer handling robots, other wafers in their lot to finish at the current operation, outgassing, ect.

I am outside my wheelhouse here (if I mess up Fred Chen knows what to do ;)), but it depends on the exact dual patterning technique that is used. Some methods require etch and ash steps between exposures. Others have multiple exposures back to back.

With TSMC you can get an ultra-super-hot lot -- basically one that is "hand-carried" through the line, everything else has to get out of its way so it never waits for anything -- but there are a *very* limited number of these available per month because they mess up the scheduling and the productivity of the entire line drops, and they're quite expensive... ;-)

A recent run like this in 5nm cost us $2.5M to shave 10 days off the TAT... :-(
 
With TSMC you can get an ultra-super-hot lot -- basically one that is "hand-carried" through the line, everything else has to get out of its way so it never waits for anything -- but there are a *very* limited number of these available per month because they mess up the scheduling and the productivity of the entire line drops, and they're quite expensive... ;-)

A recent run like this in 5nm cost us $2.5M to shave 10 days off the TAT... :-(
I’d love to hear more from TSMC customers. Are you generally happy with their service other then obviously having to pay a premium for process leadership? How does the experience compare to Samsung?
 
What’s the incentive for digitimes to generate ‘fake news’ repeatedly?

It’s difficult for me to believe that they are crudely accepting payments from competitors, though I haven’t met any of their staff personally.

They’re not a mass market publication, but instead publish for a specialized audience. Presumably they understand credibility and trust is easily lost but difficult to acquire.
 
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What’s the incentive for digitimes to generate ‘fake news’ repeatedly?

It’s difficult for me to believe that they are crudely accepting payments from competitors, though I haven’t met any of their staff personally.

They’re not a mass market publication, but instead publish for a specialized audience. Presumably they understand credibility and trust is easily lost but difficult to acquire.
Digitimes wants to drive traffic and clicks. They used to me more reputable then they are today.
 
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