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Equivalent ASIC and FPGA designs

vibeguy

New member
So I have two questions, and these are kinda hefty so I apologize for that

Q1: If we use reprogrammable FPGAs to test implementations of IP, can an ASIC be designed and manufactured that looks almost identical; and vice versa: if we have an ASIC with known layout, is it possible to implement that in an FPGA with the same layout? My thought is that the fixed logic blocks within an FPGA and routing through the switch matrices mean they will never be the same but I wonder if there's a way to get something close.

Q2: If we design a circuit implementation inside an FPGA, and only use a certain fraction of available blocks, how weakly are the unused blocks connected with the rest of the circuitry? For example, if power analysis is performed on the FPGA, how much will the unused parts of the chip affect the results? Love to hear some thoughts!
 

Daniel Payne

Moderator
A1: Yes, an FPGA design can be migrated to an ASIC. The physical IC layout of an ASIC and FPGA are totally different, so there's no concept of layout re-use between the approaches.

A2: You choose an FPGA array size based upon the size of your design, with a goal of leaving as few un-used gates as possible. The un-used gates have little effect on your standby power.
 

vibeguy

New member
A1: Yes, an FPGA design can be migrated to an ASIC. The physical IC layout of an ASIC and FPGA are totally different, so there's no concept of layout re-use between the approaches.

A2: You choose an FPGA array size based upon the size of your design, with a goal of leaving as few un-used gates as possible. The un-used gates have little effect on your standby power.
Thanks for the quick response Daniel!
For A2, what about the effect on the dynamic power of the system? would one expect somewhat of a constant margin difference in power usage?
 

Daniel Payne

Moderator
Dynamic power usage in an FPGA for unused gates would also be minimal. There are many ASIC service companies that can provide you a quote for migration, and explain the subtle things to look out for.
 

Simon A

New member
A general suggestion that might not suit you - for a product’s initial run where a high per-part cost might be bearable you can use IP-secure ‘hard-programmed’ fpgas from several vendors - the implementation risk is then minimal - and you could even switch back again. Power saving in unused fpga blocks depends on the vendor, but if nothing is toggling then there is only the clock distribution power. If this can’t be disabled, maybe it can be driven by your slowest clock.
 

Karl S

Member
Q1: If by "looks the same" means the physical layout, then absolutely not. FPGAs are LUTs, flip-flops, embedded memory, and built in functional blocks. ASICs are built from the ground up, totally custom with none of the above.

If "looks the same" means that the functions are identical then the answer is yes.

This kind of highlights the fact that HDLs for design entry was a bad decision, probably because of the need for sim ulation.
 

Karl S

Member
So I have two questions, and these are kinda hefty so I apologize for that

Q1: If we use reprogrammable FPGAs to test implementations of IP, can an ASIC be designed and manufactured that looks almost identical; and vice versa: if we have an ASIC with known layout, is it possible to implement that in an FPGA with the same layout? My thought is that the fixed logic blocks within an FPGA and routing through the switch matrices mean they will never be the same but I wonder if there's a way to get something close.

Q2: If we design a circuit implementation inside an FPGA, and only use a certain fraction of available blocks, how weakly are the unused blocks connected with the rest of the circuitry? For example, if power analysis is performed on the FPGA, how much will the unused parts of the chip affect the results? Love to hear some thoughts!
@Q1:
"My thought is that the fixed logic blocks within an FPGA and routing through the switch matrices mean they will never be the same but I wonder if there's a way to get something close."
No, not even close. There are 2 HDLs, VHDL and SystemVerilog/Verilog totally different. FPGA logic is implemented in LUTs while ASIC is implemented in Logic Gates/MasterSlice.
On the other hand, the function can be identical, the ASIC clock frequency typically higher.

My question is "Does it matter?"

@Q2: Synthesis only connects the block input clocks after placement, and only if the block is actually used. Therefore only connected blocks can toggle and dissipate power. The clock tree does dissipate power and is implementation dependent.

Emulation is for functional verification and needs to be done before ASIC build.

My question is "Does it matter?"
 
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