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Does the Micron layering technology have value in other semis?

My (contrary) prediction is that scaling will happen by chiplets flipchipped onto 350nm (calculate for skin effect), and fast turnaround minifabs that mimic the TSMC 40g process (my personal favorite) that allow ASICs to infiltrate the power hungry sloths (the 4 letter F word). Less SOC, more SIP. Less 3D, more 2D. Higher recurring, less NRE.
This discussion was about if Micron's NAND stacking capabilities would revolutionize semis as a whole or just NAND flash. As for "ram chiplets" there is no such thing. There are RAM dies that can be packaged with other dies in a DIMM. They can also be put inside a 3D stack of DRAM dies (HBM). You can further stack these HBM dies onto an interposer of some kind to lower latency. Finally you can just stack the DRAM package(s) ontop of another logic package (think products like lakefield). None of these techniques is special or new though and has been done for years. All of these are also with regular DRAM dies in a slightly different package, rather than some special chiplet technology.

The industry would not be moving to CFET if there was a thermal runaway problem or a massive decrease in PPW. For this reason I have no reason to doubt the thermal issues are manageable for stacks of a few layers.

Already being done by just about everybody for years. As for what I was talking about: I was talking about if some CFET decendent or some parallel development could allow for stacking dozens rather than just 2 device layers like CFET, that would make ALL prior logic nodes irrelevant besides for things like power electronics. I wouldn't be surprised if doing so required some beyond CMOS technology. However my point was that if logic could ever find a cheat around device scaling like NAND did, then logic could enter a cost per FET scaling era comparable to what we saw in the 60s and 70s with the invention of the IC.

I don't recall seeing this technique being discussed by others, and to be honest I don't really understand the value prop since the array logic is already on the bottom for traditional NAND (imbedded in between the BOL). What benefit is there to breaking that device layer out onto another wafer and then bonding that to your wafer with your NAND? Seems like a more complicated way to have the same result.
I just saw an article saying Kioxia's new 218 layer process is two bonded wafers.
I had to ask. HBM sounded so nice. We will stick to 130um bump pitches and serial interfaces. Thanks!