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Previously the fastest hot lots I found on a leading-edge process are around 30 to 40 days faster than a normal schedule. Now I heard that ultra-hot lots exist which make the journey in a month (80 to 90 days faster than regular).
Previously the fastest hot lots I found on a leading-edge process are around 30 to 40 days faster than a normal schedule. Now I heard that ultra-hot lots exist which make the journey in a month (80 to 90 days faster than regular).
As far as I remembered, hot-lot, super-hot-lot, super-super-hot-lot are defined as days/masking layer. Different designs might have different metal layers and the total cycle time will be different. Hot-lot typically means when lot arrives at tools, it will be the one with highest priority. Super hot lot will be the tool to be used for next step will be stand-by waiting wafer arrival. Super-hot-lot will be the lot with dedicated person handling it to avoid any delay in the processing. Hope it is helpful.
I did find some notes on SHL for automotive chips that halved the process time in 2021 but those parts were in a process with only 2 months normal.
I am assured that a month is still possible for major customers on important lots, but it seems like the amount of disruption to do that on a 4-month normal must be very expensive.
I know it is possible to get the masks made very rapidly. A couple of days delay, and they can pipeline mask production in order of need. Again, for some cost of displacing other work.
I'm pretty sure it is nothing close to 100 masks. Would be fascinated to see data / authoritative blog proving me wrong. Last I heard was more like 40, and maybe a third of those are the difficult lower layer masks.
I know it is possible to get the masks made very rapidly. A couple of days delay, and they can pipeline mask production in order of need. Again, for some cost of displacing other work.
I'm pretty sure it is nothing close to 100 masks. Would be fascinated to see data / authoritative blog proving me wrong. Last I heard was more like 40, and maybe a third of those are the difficult lower layer masks.
NAND layers are uniform and featureless, not individually masked. That is their economic (and yield) advantage. They stop every 100 layers or so to add a stabilizing pattern which keeps the vertical etch from drifting on very tall stacks,
There is some conventional CMOS underneath, probably with complexity similar to 28nm planar, then 200+ pairs of featureless layers with occasional stabilizer, then at the top the pattern is applied for etching holes straight down through all the layers, and some final metals are added.
OK, but my information came originally from end users who just counted the days until their chips came back after tapeout. The calendar delay is all they care about.
Exact meaning is likely different per foundry. In order to maximize throughput lots are queued at machines so that the machines always have work to do.
Term I have seen is for a hot lot to be put at the top of the queue and ultra hot lot is for stopping processing new lots from of the queue and let the machine idle til the ultra hot lot arrives. The number of ultra hot lots will thus be very limited as it reduces throughput. So I assume it will only reserved to the 'important' customers and cost an arm and a leg.