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Combination Optical Electronic Chip

Arthur - thanks. You caught an application I had missed in Lighting up the cloud - the external memory interface. Since DDR is coming to the end of its extensibility, a photonic interface to external memory makes a lot of sense. Of course if you can package the DRAM in a 3D stack with wide-IO, no need for photonics perhaps? This is less obvious if the integration is 2.5D (more impedance in the traces through the interposer). And of course integration in package only works if you know up-front how much DRAM to package. So indeed a photonics interface could be quite appealing for many applications.
 
Bernard , there's a physical limit on how much memory you can put on top of a chip , maybe 512MB according to some research paper . That's not enough for many systems so it'll probably serve as a large cache.

The second option - using better serdes , Kandou recently released an interface IP that enables 1tbps over a few mm (fitting for 2.5D). They aim at connecting 512GB of memory at 4tbps.

I think those two(together with cache compression( can buy you a lot of breathing space , maybe to the point that processors would become the bottleneck again. and even without that , it might be sufficient to large share of systems.

But i'm sure IO would provide a very large market to silicon photonics . many kind of servers are IO limited anyway.
 
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