Chip Design with Deep Reinforcement Learning from Google

[Daniel Nenni]

The media is all abuzz with the Google white paper on AI and EDA:

Chip Design with Deep Reinforcement Learning

ai.googleblog.com

This is above my pay grade but from what I know their description of how a "training set" of existing block placements is used for future block placement tasks is pretty primitive. Specifically, there is no feature to incorporate timing-driven cell placement criteria -- timing-driven placement (TDP) has only been around for 25 years.

Both Synopsys (Fusion Compiler) and Cadence (the new iSpatial) have also added TDP features into netlist synthesis algorithms, correct? The Google paper assumes an existing synthesized netlist (with no mention of path timing).

I'm hoping others will chime in here. I will be looking into this further so stay tuned....

 

[Karl S]

Did I just see the words "path delay"? This is just another example of digging the hole deeper when it is already too deep.
It simply does not make sense to be designing at such a low level.

Micro-programming and LUT approaches are far better than synthesizing everything from cells. It is simply reading a high speed memory which can produce every Boolean function of whatever number of address bits of the memory. Then the path delay is determined by the number of RAM blocks in the path. But then Boolean logic design was abandoned when the idiotic notion that "Verilog can be simulated, therefore it must be used for design entry". Verilog is for synthesis, not logic design. Spreadsheets are used to connect modules because Verilog is incapable.

Yeah, but do I know a better way? 'deed I do! OOP was developed to define classes for function an to interconnect those classes. And arrays are everywhere. So what? RAMs are arrays. And there are even dual port arrays when open up a lot more possibilities.

It is time to bring back the fun of logic design.