Best #48DAC Trip Report Gets an iPAD2

Daniel Payne · Jun 14, 2011

Synopsys, ARM, Samsung, Globalfoundries (Part 1 of 2)

Intro
The 28nm nodes is ready with foundry silicon, IP and EDA tools. Tuesday morning at the DAC breakfast I learned more about the 28nm eco-system.
View attachment 1284

Notes
Why 32/28nm?<?XML:NAMESPACE PREFIX = O /><O< font O<>
- Lower power, high integration requirements, mobile applications<O

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What is Ready?<O

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- IP is qualified (ARM, Memories, Foundation IP, SNPS IP, PDKs)<O

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- August 2010 SNPS and GF at 28nm<O

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- June 2011 SNPS and ARM at 28nm (A15 core)<O

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- June 2010 Samsung at 32nm with SNPS tools<O

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- Common Platform – Lynx tool flow is ready, January 2011<O

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- June 2011 GF ready at 28nm<O

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- Samsung qualifies 28nm<O

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- Samsung at 35 tape outs at 32nm to date<O

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Anna Hunter, VP Samsung<O></O>
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Technology Roadmap<O

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- 32nm LP: ready, HKMG process<O

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o SRAM at .149um*um, tiny size<O

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o Good yield at 86%<O

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o Matches SPICE results<O

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- 28nm LP: ready<O

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o Same HKMG as 32nm node<O

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o Works with ARM IP and SNPS tool flow<O

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- 28nm LPH: under development (low power, plus higher performance modules)<O

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o Will be up to 50% faster (with more leakage, 2.3X)<O

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o Same HKMG<O

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o Added strain to silicon<O

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o Shuttles starting now<O

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- 20nm LPM: in development, PDK evaluation now. Ready by end of 2012.<O

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Lynx – flow of SNPS tools and IP management, used by Samsung internally too<O

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ARM CPU – 45nm >1GHz on Cortex A9<O

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- 32/28nm >1.35GHz on Cortez A15<O

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- 28nm LPH, >2.0GHz Cortex A15<O

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IP Portfolio – High Speed, Memory, Mixed Signal<O

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- ARM, SNPS<O

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Going from 45nm to 32nm more than 50% improvement in SRAM bit cell size<O

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Turn key solutions from Samsung<O

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- Design, Fab, Wafer Sort, Assembly, Final Test<O

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- Working on TSV technology for higher integration on packaging<O

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MPW – Run every quarter for 32nm and 28nm<O

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- Will start 20nm in September<O

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Fab sites – Korea (20nm), Texas (40K wafers per month)<O

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Jim Ballingall, VP Marketing at GF<?xml:namespace prefix = o ns = "urn:schemas-microsoft-comfficeffice" /><o></o>
- AMD lead product used HKMG technology, quad core CPU with GPU integrated, 500GFlops, for notebooks<o

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- Llano powered laptops later in June<o

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Super Low Power – 28nm SLP (doesn’t use stressing), about 2.3GHz<o

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High Performance Plus – 28nm HPP (uses stressing), about 3.1GHz<o

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Global Solutions – Design Solutions, Technology, Design Infrastructure<o

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IP – in place<o

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Fabs – New York, Germany, Singapore<o

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MPW – 4 shuttles in 2011<o

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20nm – working with Common Platform partners, area scaling of 50% from 28nm<o

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</O

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Daniel Payne · Jun 14, 2011

Synopsys, ARM, Samsung, Globalfoundries (Part 2 of 2)

Dipesh Patel, VP Engineering, ARM Physical IP<?xml:namespace prefix = o ns = "urn:schemas-microsoft-comfficeffice" /><o></o>
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Consumer demand for smart devices, short life cycles (SmartPhone, Tablets, Internet screens)<o

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Processor speeds: 1GHz to 1.5GHz<o

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SOC Memory: 600MHz to 1.2 GHz<o

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How power efficient?<o

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How is the layout density?<o

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Standard Cells: multi-channel, multi-vt (4) libraries<o

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Memory Compilers: single port, multi port, ROM <o

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7 families to choose from<o

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28nm libraries nominal VDD of 1.0V<o

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<o

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Processor Optimization Package (POP)<o

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- Physical IP<o

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- Reference flow, documentation, guidelines<o

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- ARM certified benchmarking<o

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Cortex A9 – 1.3GHz performance now<o

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Silicon Validated – created Test Chips for GF and Samsung at 32nm and 28nm nodes<o

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Fab Synch – migrate any design from one fab to another one<o

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Ready to Start – http://designstart.arm.com/ <o

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Andy Potemski – Director of Global Technical Services, Synopsys<o></o>
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Lynx Design System – About 2 years old, design system of silicon realization tools<o

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- Off the shelf productivity<o

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- A core flow for building an ARM Cortex A9<o

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- Configure Flow with High Performance Libraries and IP<o

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o Use DesignWare or 3<SUP>rd</SUP> party IP<o

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- Optimize the methodology for design specific needs<o

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- Optimize the design floor plan in the context of the full chip<o

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o Quad core A9 floor plan<o

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o Explore and optimize<o

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- Optimize performance and power<o

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o Detailed routing<o

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o Trend analysis of design metrics like power, area, speed<o

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- Optimize the design flow turn around time<o

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o Track execution of all tools<o

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o Analyze the profile of each tool<o

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o Identify tool bottlenecks<o

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<o

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Q: The ARM brochure says up to 25% higher performance or 80% less power. Can I get both?<o

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A: That’s very difficult. It’s really a tradeoff that you have to choose between.<o

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Q: How will work on 28nm help 20nm, especially in light of litho effects?<o

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A: We’re collaborating early in the development of 20nm to learn from our Common Platform partners. Double patterning is needed for 20nm. Expect to see a 50% improvement in density going from 28nm to 20nm node. Computational lithography required on 20nm. Another level of litho complexity make architectural exploration a challenge. Trying to minimize the number of double patterning layers required.<o

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Daniel Payne · Jun 14, 2011

Blue Pearl at DAC

Intro
It's all about analyzing RTL and creating timing constraints at Blue Pearl, so I stopped by their booth on Tuesday morning to get an update on what's new for 2011.

View attachment 1287

Notes

What’s New in 2011 at Blue Pearl Software<o

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New designer experience, ease of use. Brand new GUI.<o

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Work with RTL to synthesis tools to get best timing in your layout.<o

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GUI – windows 7 and Linux, same look and feel.<o

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- All new in 2011<o

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- Inline help<o

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Blue Pearl Analyze – Linting, race checks,<o

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- Demo: support languages: verilog 1995, 2001, 2005, System Verilog, VHDL 2008<o

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- Read your libraries<o

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- Modules can be grey box or black box<o

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- Clocks can be automatically identified or manually setup<o

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- Schematic view auto generated based on your source code<o

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o Cross probe between RTL and schematic view<o

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o Quick browsing of hierarchy<o

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- About 250 checks are run on the source code<o

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o LInting<o

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o Low power<o

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o Timing constraints<o

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o DFT<o

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o CDC<o

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o Etc<o

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- Visual Verification<o

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o 200K gate design<o

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o Lint, structural checking, CDC analysis, CDC identification, <o

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o Using FlexLM for licensing<o

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o False path, multicycle paths<o

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o Only 45 seconds needed on a laptop<o

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o Faster than others who synthesize to gates, instead of staying at RTL level<o

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o About 10X faster than other approaches (Atrenta)<o

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o Run the tool from the bottom up<o

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o All the CDC unsynched paths are shown in text list, clicking creates a schematic view<o

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o Designer decides what to do with the violations to accept or ignore<o

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o User can filter the messages, warnings, errors (Use rules, patterns, modules, names, severity)<o

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o <o

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Blue Pearl Create – <o

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- Creates an SDC file automatically<o

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- All false paths are displayed in a tree view and schematic view<o

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- Assertions are shown for each false path<o

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- An audit trail explains why the control values are creating a conflict<o

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- The SDC file will help other tools (STA, Synthesis, ATPG) to reduce their run times<o

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- Can save weeks of time compared to manual SDC constraint generation<o

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- 200K design run in minutes<o

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- Customers: Microsoft, KLA, Cypress Technologies<o

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Usage: Block level designs, run on PC or Linux boxes<o

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Users: IC (Constraint generation), FPGA (Help on large designs like Virtex with 10M gates, PC and Windows. Find Clock Gating opportunities), IP (want more tool flexibility)<o

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Version 5.0 (Blue Pearl Software Suite)<o

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Daniel Payne · Jun 14, 2011

Tanner EDA at DAC

Intro
For 22 years now Tanner EDA has been in the business offering tools for AMS and MEMS designers. I learned what's new at DAC on Tuesday morning.

View attachment 1289

Notes
Nicholas Williams – Director of Product Management<o

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Tanner EDA front end: S-Edit integrates with Berkeley Fast Analog Simulator<o

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W-Edit – is the waveform viewer<o

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Who is Tanner – full suite for custom IC design<o

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- 22 years in industry<o

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- AMS focus<o

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- First on Windows (also Linux)<o

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- 20K licenses, 67 Countries<o

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S-Edit – Schematics (Import Mentor and Cadence legacy data)<o

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- Cross probe between schematics and layout<o

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- Checking <o

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- Launch simulation, make measurements<o

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Berkeley Analog Fast Spice (AFS)<o

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- About 5 to 10X faster than SPICE<o

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- 10M element capacity<o

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W-Edit – setup measurements<o

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- Scripting for sophisticated measurements<o

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- Built in measurement functions<o

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Layout editor – L-Edit<o

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SDL – schematic driven layout<o

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HiPer DevGen – layout generators<o

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HiPer Verify – Netlist extraction tool (Takes Calibre or Assura decks as inputs)<o

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HiPer PX – parasitic extraction<o

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Why choose Tanner?<o

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- Economic price<o

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- Installed base<o

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- PDKs<o

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Why not your own Fast SPICE?<o

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Easier to partner with a leader already.<o

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John Zuk<o

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Last year – Hiper DevGen (Dublin based, IC Mask)<o

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- This year added: Resistor arrays for matching, adding mosfet array generators, adding current mirrors<o

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- Focus is on analog blocks<o

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SDL – read in netlist analyze it, find current mirrors, use Hiper Devgen automatically<o

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Interactive DRC – close enough to final rules, then HiPer Verfiy in batch to complete the layout verification<o

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Open Access – in integration now, L-edit is first, S-edit is next. PC –based we donated technology that they didn’t even have. <o

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- Took more effort than anticipated.<o

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- Working with Si2 to define what OA should be<o

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- iDRC and iLVS are in the future, after L-edit and S-edit, waiting to be embraced<o

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- IPL Constraints – looking at that as well, designer notes, will be part of S-edit<o

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- V16 is due in October and will be the first to support OA<o

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iPDK – Looks more practical than Open PDK<o

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- In V17 this would be supported in 2012, beta by June 2012<o

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Resell BDA tool – 1[SUP]st[/SUP] line of support, <o

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OEM – parasitic extraction tool (Tuo Delft in Netherlands, HiPer PX extraction)<o

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- Hiper devgen <o

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Tanner version – scaled down version limited by processors and total elements, lighter version, token based<o

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- Worldwide sales agreement<o

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- First copy to be sold very soon<o

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Fiscal Year – 140 new customers in 2011<o

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Greg <o

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3D field solver as an upgrade<o

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V16 – multi user now available<o

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OA – realtime collaboration on the same database<o

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Daniel Payne · Jun 14, 2011

Extreme DA at DAC

Intro
Over the lunch hour on Tuesday at DAC I met with Emre Tuncer, VP – Product Engineering & Applications and heard about extraction and timing analysis.

Notes

View attachment 1292

GoldX – parasitic extractor. Fast extractor, recently announced, all new technology, early customer adoption. One customer deploying it in 40nm, soon to be 28nm.
- Sold stand alone.
- Fast run times.
- Scalability, more cores better speed.
- Within 2% of a 3D field solvers on average. Mean is 1.5%, sigma is 1%.
- SPF timing differences are within 5ps.
- Cell-based extractor (not transistor level tool, stay tuned for device extraction)
- Extract each block, then stitch SPF files together at the top level
Focus –static timing analysis (Engine is statistical), reduce the turn around time, less pessimistic models (less fixing).
TSMC – Gold Time is endorsed for Reference Flow (Statistical Timer).
Prime Time, why switch ?
- Faster turn around time
- As good or better than SPICE accuracy
- Better reductions than Prime Time, reduce the amount of pessimism

Gold Time – out for awhile now, OCV is important and short turn around times
- Broadcomm
- Qualcomm
- Xilinx
- Not working as closely with Common Platform partners yet, mostly TSMC
- Quick run times using efficiency, MT

Daniel Payne · Jun 14, 2011

Synopsys IC Validator at DAC

Intro
At DAC last week I visited the Synopsys demo suite to see what's new with IC Validator.

View attachment 1294

Notes
Stelios Diamantidis, PMM
- In-design physical verification
- Sign-off reveals thousands of late stage DRC violations
- 28nm has 1.5K rules, 15K runset sizes
- Metal Fill changes timing
- The DRM can be changed throughout the life of the process

Timing Closure – can be too slow, too many iterations, too time consuming
- A new methodology is needed

IC Validator – verify as you go, early, not at the end of routing
- Run during: Floorplan, P/G, Placement, CTS, final route

In-Design PV: Metal Fill
- Foundry runset used by IC Compiler
- Evaluate timing of critical nets, timing aware metal fill
- Automate ECO process, identify shorts, push route out, comply to DRC rules
- Example of timing driven metal fill evaluation
o Renesas: 6X faster TAT using ICV with ICC
o AMD: 30 minutes to complete Metal Fill, 580K nets

In-Design PV: Signoff DRC
- Incremental Checking (analysis by Layer, Area or rule)
- GDS Merge – remove cell boundaries (full mask checking on demand)
- Automatic DRC Repair (highly localized, router driven), router told where to correct violations
- ST: Used the flow to find and fix 340 violations in just 35 minutes
- TI: Up to 100% auto fix rate , Automatic DRC Repair (ADR)

Smart Error Management
- Milkyway Intgration (direct access to properties)
- Error categorization (automatic linking of violations)
- Interactive filtering (querying or sorting of violations)

Chris Grossman – Corporate AE
Demo of IC Validator, live
- Start with IC Compiler, DRC checking shows 20,330 violations
- Stepping through each DRC violation graphically, decide how to fix DRV violations with scripting or manual efforts
- Another way is to use ICV (DRC checking) inside of ICC (P&R)
- Results of DRC checking shows only 3926 violations, not 20,330 at the end of detailed P&R
o Filter the DRC violations: P/G Nets, Clock Nets, Signal Routes, User Routes
o Re-run just one rule at a time, re-run rules in one rectangular area at a time
o You can leave the floorplanning stage knowing that you are DRC clean
o After checking DRC after PG, it’s time to run DRC after Clock Tree Synthesis (CTS)
o Now only 16 DRC violations found (Found a RAM placement too close to a VDD)
o Run MergeGDS to see where this RAM instance has a DRC violation
o After CTS time to run detailed routing, found only 143 DRC violations now

Summary
- Run In-Design PV at each stage of physical design, not at the end of detailed routing
- In-design physical verification saves weeks of time over the old implement then verify approach
- IC Validator: pre-routing checks, routing checking, automatic repair, timing aware repair
o Next release: 1.5X faster DRC runs, 1.5X smaller fill size, 3X less fill memory
o 20nm: double patterning required, native DPT coloring engine, In-Design decomposition checking
o Equation-based DRC
o Debug Productivity: will have a new LVS graphical schematic viewer, LVS equivalent error browser, graphical runset debugger
o Advanced Nodes: fill-to-target (correct by construction), pattern matching (Prevents manufacturing limiting layout patterns)

ICC - Has 60% market share in P&R

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simguru · Jun 15, 2011

48th DAC Report

[Also thanks for the iPad Dan - my wife is making good use of it]

I like to do as much of DAC as I can, this year I managed to attend from Tuesday through to Thursday lunchtime. Between the major items below I wandered the exhibit hall (but don't have much to report there).

On Tuesday morning as I picked up my conference material I spotted a free breakfast courtesy of Accellera, so I popped in for bite to eat and coincidently won the raffle for an iPod Shuffle. I think the focus of the breakfast meeting was UVM (more of that later).

The Tuesday keynote by Lisa Su was definitely worth sitting in on, and a little bit of an echo of last year's talk by Iqbal (47th DAC Keynote: Arshad). I was encourged by her request for better tools in areas of EDA that I work in. All the keynotes will be online eventually.

I wandered around the exhibits for a while and sat in on "Hogans Heroes", but I don't remember much about it.

I then had lunch courtesy of Synopsys for a talk on "Smart Verification", which was mostly about what folks are doing with VCS these days. Nothing particular springs to mind about the material presented.

In the afternoon I sat through the "It's All In The Models..." technical session - generally good papers, and followed that with half the "Analog and Mixed-Signal Design in an Uncertain World" - I left during the paper that won best paper (so maybe I should have been paying more attention) to attend the WACI session which was less weird than expected and introduced me to PUFs.

The Synopsys "SPICE Up Your Chip" dinner session was interesting in that (as suspected) Spice/analog methodology doesn't seemed to have become much smarter in the last decade. I was sitting at the same table as the Solido guys, who got a mention for their efforts in reducing the number of Spice runs you have to do.

The Cadence/Denali party was generally good fun, though maybe a bit crowded and loud inside the building, outside it was possible to have a conversation - I had a few, the details of most escape me now, but I remember betting Steve Liebson that DAC would be subsumed into the Embedded Systems Conference in the not too distant future. Don Draper of the Hot Chips conference seemed to be planning a coup at the IEEE in order to get more democratic representation. Bumped into a young woman who I had met at SFO on the way down, who was hanging out with the GRID Simulation team, so got I introduced to some more folks doing Spice simulators (how many are there?).

Wednesday kicked off with the Synopsys "Interoperability Breakfast", followed by a panel session on EDA Research.

The research discussion was interesting, with some criticism of students for repeatedly solving the same problems. My own pet peeve is that not much work gets done in a way that you can build on it. Peggy Aycinena asked some pointed questions (see Twitter).

I sat through Gadi Singer's keynote on "The Imminent EDA Transformation", but things looked pretty much the same after it was over, so I'm assuming this is "imminent" on a geological scale rather than conference level - particularly given the evidence from the glacial rate of change in analog (Spice) methodology.

John Aynsley of Doulos gave a good lunchtime talk introducing folks to UVM. My only comment would be: why are we not just doing this in C++ so it would work with SystemC too? - but that's not John's fault.

The next thing of significance after that was the panel session "How to Verify Billion-Gate Designs". I asked the question "what about the analog aspects of digital design - like power management", and the panelists seemed to be confused by it. Otherwise there was a good discussion of the problems and some of the solutions.

The Wednesday evening reception (replacing the DAC party) was not a great event. I think the concept was good, it just needs some more work. The Tuesday night reception looked more fun but I had to bail out early to get to the AMS dinner.

Thursday was (of course) somewhat quieter with the exhibits having gone, however the 3-D and "ESL HW/SW Verification: A Reality Check" panel sessions were well attended - with the ESL session getting fairly controversial at times.

The keynote by Dharmendra Modha was interesting, well attended and probably indicates where the R&D money is going (if not to EDA), and probably gives a good indication of how close we are to producing machines with the complexity of the human brain.

Conclusion: DAC is still worth attending as a technical conference. I thought the panel sessions were generally good and there were some interesting papers, although I would agree that the 15min format might be on the short side - but there was plenty of opportunity to talk to the speakers.

[I was a bit peeved I could not fit in the Smart Grid Workshop day - if you did can you write it up?]

harpoon · Jun 17, 2011

yippee ... I just received my ipad2 ... thanks to D.A.N. for shipping it to me.

all the best semiwiki

Daniel Payne · Jun 17, 2011

Berkeley Design Automation at DAC

Intro
Simon Young, Product Marketing manager at BDA gave me an update at DAC last week on their circuit simulator, Analog Fast SPICE (AFS).
View attachment 1315

Notes

Quarterly release: 2011 Q2 now

Speed Improvements: Still 5 to 10X speed improvement over other SPICE tools

Multi-Threading – 2 to 4 X improvement using 4 to 8 cores.

Device Noise – three ways to compute noise: Transient, PSS/pnoise, Oscillator
- Comparing transient noise with PSS they agree with each one to one (Cannot do that in Spectre, they are different values)

Customers – About 120 logos this year

Distributors – Canada, India and Israel added in past year

Competitors – Spectre, FineSIM, Eldo, HSPICE

Customers – High-speed I/O, PLL/DLL clock synthesis and recovery, data convertors, delta-sigma modulators, full-circuit RFCMOS ICs, memories.

Capacity – 10M elements

Summary
BDA coined the product category Analog Fast SPICE to denote a circuit simulator that is SPICE accurate with a 5X to 10X speed improvement over traditional SPICE algorithms. The other EDA vendors claim to have caught up to BDA's tool, however you'll just have to benchmark it on your own circuits to determine the speed, accuracy and capacity claims.

I continue to see BDA in growth mode by adding new staff, so their products must be selling well around the world.

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Daniel Payne · Jun 17, 2011

One Trillion Transistor IC Layout at DAC

Intro
Micro Magic was the only company at DAC that showed an IC layout editor with 1 Trillion transistors loaded in it, wow.

View attachment 1318
Karen Mangum

Notes
I chatted with Katherine Hays, a 12 year veteran of Micro Magic about what was new at DAC this year.

Max-3D – Can handle stacked wafers with TSV
- Gary Smith’s list of must-see for 3D
- New for 2011: 3D Floor planner
o Mostly a manual process to do TSV on two or more stacked dies
o 3D Floorplanner automatically finds all thos places
o Autoplace 3D vias (placed on edges in this demo because of density of SRAM on top of processor)
o Demo with 3 stacked die, also autoplace 3D vias
o Tezzaron – customer using Max 3D, designing 3D stacked wafer designs. Doing a 7 stacked chip design.
o 3D DRC – Magma has a tool, you can launch Magma inside of Max-3D and view the results interactively
o Pricing:?
View attachment 1317

OA – we can read and write it

Large designs – Virtuoso cannot move or work on the largest designs, so it’s time to consider using Max or Max-3D

Max – demo with 1 trillion MOS devices at DAC this year
- Tezzaron read in 100GB GDS II layout database into Max

Customers – Most will not be mentioned because of corporate policy.

Summary
We all know that the big three EDA companies have IC layout editors (Cadence, Synopsys, Mentor) but this lesser known EDA company has capacity and 3D features that I don't see anywhere else.

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Daniel Payne · Jun 17, 2011

EDA Interoperability at DAC

Intro
My Wednesday breakfast at DAC last week was at the Interoperability event sponsored by Synopsys. The Synopsys moderator was so jovial that he reminded me of Jerry Lewis, I was relieved when the guests gave us an update.
View attachment 1321

Notes
Interconnect Modeling

- Open Source Interconnect Technology Format (ITF)

o Used by Star RC

- Modeling parasitic of interconnect
- Interconnect Modeling Technical Advisory Board founded, meet twice per year

o Program of IEEE-ISTO
o Andy Brotman, VP Design Infrastructure at GF

IMTAB – foundry perspective
Design starts are slowing in number for each new node (although each new node has more devices)
Need to avoid risks, ensure 1st silicon success
Mistakes are more costly (NRE)
Parasitic variation increases at 20nm, more analysis required
Layout effects need to be simulated earlier
Best in class extraction tools are a must
Standard interconnect tech file used (Star RC, F3D, …)
New layout effects: Orientation dependent width bias

o Rich Laubhan, Engineer and Manager of Signal Integrity at LSI Corporation

User perspective (Used Star RC for 13 years now)
LSI products: HDD controllers, SSD controllers, RAID adapters, networking
Producing 65nm, 40nm, 28nm chips
Many signoff PVT/RC corners
• No real single corner to simulate
Many modes to simulate: functional, scan, BIST, TDF
High speed designs: 500MHz to 2GHz clocks
Can have 200 clock domains
Hierarchical designs with 20M instances
Plot of transistor feature size and number of metal layers (12 layers now)
ITRS plot: total metal interconnect on a chip over time, more resistive effects
No standard test structures to measure R L C values
We use Charge based capacitance measurement (CBCM)
More wires, higher resistance, metal fill effects: designer challenges
LSI Design Flow: Tech File and Design input to Parasitic Extraction, output a SPICE Or SPEF file
• Tech file: cross section, dielectrics, vias, R L C values
Tech File Complexity: IC Cross section with 12 metal layers, dielectrics
• Longer qualification time to meet accuracy goals
• Variation in process causes variation in R L C values
ITF Open source – provides a proven format with support from 130nm to 20nm
ITF Extensions proposed
• Quick process to get ratified
• Layout dependent effects
• TSV
• 28nm and 20nm effects
Desire to use fewer EDA tool formats to keep costs lower
• Changed extraction tools three times for last three technology nodes
Challenges
• Agreement on test structures
• Accurate results

Tenzing Norgay Award
- Surpass common levels of interoperability
- Contribute to overall industry advancement
- Provide a new view of the future
- 2011 Winner: Shreink Mehta
o Work on UPF, SystemVerilog
o Sun SPARC
o OVI and VHDL
o SPIRIT

IPL & Custom Design
- IPL Constraint 1.0, first standard for interoperable analog design constraints
- OPDK and iPDK are cooperating
- Vincent Varo, Process Design Kit Manager, STMicroelectronics

o Desire to reduce effort in PDK development, create one PDK not many, use across all EDA tools
o Device Library, DRC, LVS, PEX, SPICE
o Standardized input to PDK development process from all foundries desired
 Standard DRM, Device Specification format
o Challenge: How to validate an automatically created PDK?
o Mulitple methods to create a single iPDK
o Parasitic Extraction technolog file
 IMTAB, or Si2 OPEX WG
o Desire to be EDA Tool independent
o Next steps
 Automate the PDK validation process
 Design re-use and portability
 AMS design portability
 Designs that are DRC and LVS clean by construction

- Ori Galzur, VP VLSI Design Center, TowerJazz

o Largest foundry for speciality technologies
o Total of 4 foundries: Newport Beach, Japan, Israel, China
o Approaching $1B in revenues
o Power, BiCMOS, SiGe, RF CMOS, Image Sensor, Mixed-Signal CMOS, eNVM
 1um to .13um
o Specialty PDK for high voltage process
 Automatic device scaling based upon the voltage levels that you need
 ESD rules added to PCELL
 From schematics a designer gets to choose from a GUI all of the device parameters
o Average PDK has over 120 devices
o Each device can be used in: Standard, Shallow NBL, Deep epi
o All devices are voltage scalable, optimized
o Supporting multiple tool sets takes too much engineering effort
o Want one PDK to focus engineering on other value add efforts
o Choose the best foundry, best EDA tools, not locked into a vendor-specific PDK

Summary
- Demand that your Foundry and EDA vendors support iPDK

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Daniel Payne · Jun 17, 2011

Ciranova Update at DAC

Intro
Ciranova offers you an alternative for analog layout automation besides Cadence Virtuoso. Mark Nadim provided me an update at DAC last Wednesday.
View attachment 1323

Notes
New in 2011
- New GUI with schematic, layout and constraints
o Cross probing between all three windows
- Schematic for constraint entry
o Can start with a blank schematic, enter new design
o Read any native OA schematic
o See all the MOS instances in a tree, define layout constraints very quickly
o Drag and drop constraints
o Cross probe between MOS list and Schematic view
o Hierarchy supported
- Helix First Look
o Schematic and Analog constraints in, layout out
o Find in netlist common bulks, get placed together
o Easy way to create initial layout constraints, does auto grouping of layout
- New customers: Marvel
- 28nm migration is important, Helix is an easier way to conform to new design rules
o Auto placement helps on minimum rules
o Read design rules for density and Helix can push transistors apart to reach the rules
- Create many alternative layouts, Extract a netlist, use Calibre parasitics, create fully extracted netlist ready for Berkeley AFS
- Users: Initially the Circuit Designer starts, then handed off to the Layout Designer for completion
- Routing Example: pattern based constraints used, then autoroute between all the rows and columns of placed Devices
- New way to create layout constraints, based on patterns or Python scripts (mostly CAD or Circuit Designers create scripts)

Summary
Ciranova Helix is a tool that can create analog layout using PyCells very rapidly by a Circuit Designer. Demanding IC designers from the largest semiconductor companies in the world use these tools.

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Daniel Payne · Jun 17, 2011

RLCK reduction tool at DAC

Intro
Most EDA parasitic extraction tools have built-in RC reduction with no user control however at DAC I learned how Edxact offers a stand-along RLCK reduction tool for IC designers that want more control over what happens to their extracted netlists.
View attachment 1325
Daniel Borgraeve (on right)

Notes
Edxact
- Started seven years ago
- Fifteen people in the company
- Based in France
- Jivaro: RLCK reduction (RLCC) with user control of results
o Many algorithms to choose from
o Used by Aglient in their GoldenGate tool (RF Simulator)
o Used by Intel
o About 25 customers world wide (Asia, Japan, Korea, US)
o Part of TSMC AMS Reference flow 2.0
o Pricing starts at $100K per license per year
View attachment 1326

- Comanche:
o Read parasitic
o Create R values point to point, calculate delays
o CAD developers can compare two netlists (Golden versus some extraction tool)
o Parasitic analysis platform
o Used by: AMD, ST Ericsson
o Pricing starts at $100K per license per year
- Partners
o Altos (Library Characterization, used Jivaro)
o Cadence (Integrated into Virtuoso)
o SpringSoft (Integrated into Laker, can annotate parasitic into Laker)
o Mentor (read DSPF, Eldo formats)
o Synopsps (support Star RC and HSPICE syntax)
o TSMC – part of AMS Reference flow
- Runs on: Solaris, Linux, Mac

Summary
If you want more control while reducing RCLK netlists then consider looking at Edxact tools.

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Daniel Payne · Jun 17, 2011

Cadence spinout at DAC

Intro
I remember when Celestry was acquired by Cadence because that gave them a hierarchical Fast SPICE simulator to compete with HSIM. In 2007 part of Celestry spun out from Cadence and became Proplus, which now offers a SPICE simulator called NanoDesigner.

Notes
Proplus – US company, founded in 1995 (Used to be Celestry, acquired by Cadence, spun out in 2007)
- R&D in Beijing and Silicon Valley
- NanoDesigner (4 years old): SPICE tool, not Fast SPICE

o Compete with: Spectre, FInesim, HSPICE
o Accuracy is the goals
o Statistical SPICE (Monte Carlo technique)
o Customers: Not disclosed
o Pricing: Not disclosed

- IR/EM Verification

o Partnership with Grid Simulation Tech
o Customers: Not yet

Summary
I hadn't heard of Proplus before last week, so I've added it to the list of all SPICE tools on our wiki page.

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Daniel Payne · Jun 17, 2011

Reduced IC leakage at DAC

Intro
Neal Carney, VP of Marketing at Tela Innovations provided me an update at DAC last week. Their company partnered with TSMC to reduce leakage in IC designs by biasing the gate lengths on your paths that are non-critical to timing.

Notes
View attachment 1329

Why do this?
- Reduce leakage
- Increase gate lengths on paths with slack
- Recharacterize cells for change channel length, new performance
- Take the output from Primetime for paths with slack
- Our tool also has a timing engine built into it
- Fine grain optimization for leakage optimization
- Our tool does more cell swaps than other tools do
- Can swap multi vt cells as well
- TSMC has four Vt choices, but with gate biasing you have finer control than just swapping Vt
- Gate biasing doesn’t require another mask
- Optimize for: Performance, leakage, costs
- At 28nm the PowerTrim libraries should become more mainstream
- At 40nm, you can bias the gate length to optimize as well
- Another technique for 28nm is to start with 35nm then use gate biasing
- Customers can ask for design services from Tela, or ask TSMC to use PowerTrim
- Customers: LSI Logic, Melanox, undisclosed (over 50 tapeouts so far)
- Gate biasing can make the device go faster (more leakage) or slower (less leakage)

Summary
If you fab with TSMC and want to reduce your leakage currents, then consider the PowerTrim library approach.

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Daniel Payne · Jun 17, 2011

Circuit Simulation update from Cadence at DAC

Intro
In the bloggers suite I met with John Pierce of Cadence last Wednesday to get an update on what's new with circuit simulation at DAC this year.

Notes

News – market is growing, RF CMOS simulation is growing
- Show on RF (MTT – Microwave Technology ) this week, sharing a booth with AWR this week
- Recent news with Lorenz (EM tool to create inductors), they’re part of Connections program
- APS RF released on year ago (Parallel in the new engine)
- RF usability improved, able to do s-parameter analysis

Virtuoso APS – continued to improve, up to 16 cores
- December 2010 now you can go distributed, across machines
- No special setup required
- Uses more tokens
- Super Threading: multi-core plus distributed processing (multi-core per box)
- Typical usage: Two machines, 4 cores per machine

UltraSim – looking at next generation technologies
- Usability and speed improvements done and planned
- New developers added
- Did a new RF model

Modeling – how to model FInFET (Tri-gate)?
- Compact Modeling group involvement

Altos – acquired library characterization company
- Integrated with them last year, especially memory characterization
- Works with either Spectre or UltraSim or internal simulator

Growth – Altos had 11 out of 20 top semi companies for library characterization
- Good collaboration over past 12 months too (Jim Mccanney)

Spectre – New in last year is APS and distributed
- Shares models with UltraSim

AMS Designer – transistor simulation plus HDL
- Real number modeling (standard part of SystemVerilog) lets you model analog effects in a logic verification environment
- Did a paper at the ARM conference last year, DVCON this year (assertions plus real number modeling)
o Help ADC test bench verification
- Adoption of real number modeling is driven by the design style more than the technology
- Work with designersguide.com on training the next generation of AMS designers, classes tailored to the client and offer consulting services
- Knowlent went out of business as Analog Verification IP (too limited of an approach, not portable)
- How to influence the next generation, Universities

Parasitic Aware Design – simulation with real parasitic, as early as possible in the flow
- Quickly go from schematic to layout to extracted parasitic, better simulation results
- Virtuoso can help manage the whole parasitic flow

IMS Chips (Germany) – Used Custom Designer, then went back to Virtuoso (Feb 2011)

Wolfson (UK) – Uses SNPS digital tools, and internal analog tools. They evaluated Custom Designer but choose Virtuoso plus digital flows.

Summary
Cadence has plenty of competitors in the circuit simulation space so they continue to update and innovate their tools to stay current. Only three vendors offer an integrated co-simulation between SPICE and a widely-adopted HDL simulator (Cadence, Mentor, Synopsys).

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Daniel Payne · Jun 17, 2011

Hardware Configuration Management at DAC

Intro
Show me what has changed in my RTL or Schematic since the last time I looked. This task is now automated by Cliosoft with their new hierarchical tool called Visual Design Difference (VDD). Srinath showed me what was new for DAC.

View attachment 1331
Srinath Anantharaman

Notes
LSI, STMicro – use DesignSync for their DM but use VDD for seeing visual differences.
View attachment 1332
Visual Diff – Tool introduced just over one year.
- This year it handles hierarchy.
- Can also ignore Cosmetic Changes that have no electrical changes.
- If you make changes to your RTL design, then how do you see what has changed?
- Demo: Compared two versions of a design

o Tree widget shows the hierarchy of where to find the changes
o Expand the tree widget, see each difference in logic
o See changes in different colors
o Zoom on changes per pin or net, complete text description
o Standard feature at no extra cost for existing customers
o Can even see property changes along with logical changes

Clients: Virage – started with Springsoft Laker, then Virtuoso, now Custom Designer (stayed with Cliosoft DM throughout)

Summary
If your IC design team has two or more engineers then your job will be made easier with a tool like VDD from Cliosoft.

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Daniel Payne · Jun 17, 2011

An Affordable 3D Field Solver at DAC

Intro
Massimo Sivilotti, Ph.D of Tanner EDA showed me their 3D field solver in the HiPer PX extraction tool at DAC last week.
View attachment 1336
Notes
View attachment 1335
Tool Suites – schematics, layout, SPICE simulation, DRC/LVS
- HiPer PX: 3D Field solver

o Layers, dielectrics,
o Finite element analysis
o Boundary element methods
o 2D mode for pattern matching
o PDK – includes the info for PX extraction
o 3D viewer to see the IC Layout
o Offered for a few years now
o Extract: Devices, parasitic, interconnect
o Produces RC netlist (not L, not s-parameters), coupled C
o Take parasitic from PX extraction then view it in Schematic editor (S-Edit)
 Swap out cell parasitics by changing the view
o Run times are more limited by your simulator, not the extraction
o Built-in netlist reduction algorithms (supply a frequency range), typically the reduced netlist is 10% the size of the original netlist
o Not a multi-core algorithm yet (T-Spice is multi-core for circuit simulation)
o Developed at TU Delft in Europe, licensed technology
o Runs on both PC and Linux (32 or 64bit)
o Comparable accuracy with Assura RX

Licensing – Sentinel
- Dongles
- Commuter
- Time-based
- Rentals
- Even permanent licenses

L-Edit – used for stacked die layout with IC and Mems
- Packaging techniques to locate all pads

3D Solid Modeler
- Used for MEMS Design – have a solid modeler (air or dielectrics)
- Interfaces to Finite Element Analysis
- Optical example with mirror

Summary
Tanner EDA continues to offer affordable IC design tools, HiPer PX offers both 3D and 2.5D extraction depending on the accuracy that you need.

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Daniel Payne · Jun 17, 2011

DRC tool guns for Calibre at DAC

Intro
Across the aisle from the Mentor booth at DAC sat a DRC tool competitor to Calibre. I received an update from Randy Smith of Polyteda on Wednesday afternoon, my last EDA vendor of the week.
View attachment 1339
Ravi Ravikumar, Randy Smith

Notes
Randy Smith – CEO (February 2011) [former founder is gone]

- 1979 at HP developing internal tools
- Trilogy
- Tangent, Acquired by Cadence
- Bought 4 times
- Celestry->Cadence
- Gambit->Synopsys
- Japan consulting business

Before – big performance claims

Now – about 2 to 3X faster than Calibre while running in flat mode, PowerDRC

- Look for a new hierarchical announcement by end of year, look for a new name
- Smaller memory footprint
- Easy to scale across multi-processors
- TSMC has a reference flow, while larger companies can use a new DRC tool during design process
o 3 way NDA between: Polyteda, TSMC, Client. Tune the rule deck. 40nm deck. Takes 18 months to reach sign off, stay tuned.
- OEM relationship with AWR – single CPU limitation
- IHP – customer, AMS client at 180nm (Pricing of Calibre seems too high)
- Price/Performance – produce more results with less cost than Calibre
- Learning curve: batch oriented, easy to learn, debugging is more of the issue, something similar to RVE called RDE (still internal)
- Time based licensing, tied to the number of CPUs
- Mentor has two licenses: Flat or Hierarchical
- Polyteda will have one license: Flat and Hierarchical
- Over 40 people in the company
o R&D in Moscow
o HQ in Santa Clara

Summary
Polyteda has reset expectations about their DRC tool performance and will have to battle against the entrenched Calibre in the marketplace. Competition always benefits the EDA tool users who need every advantage to get to market quickly and have first silicon success.

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Daniel Payne · Jun 17, 2011

Circuit Simulation and IC Layout update from Mentor at DAC

Intro
On Monday evening I talked with Linda Fosler, Director of marketing for the DSM Division at Mentor about what's new at DAC this year in circuit simulation and IC layout tools.
View attachment 1342

Notes
IC Station – old name for IC layout tools

Eldo – Eldo Classic

- Cell characterization
- ST is the early customer and teaching customer, their Golden Simulator
- Widely deployed worldwide

Eldo Premier (January 2011 introduced, free transition from Eldo customers, new option, uses 2X the licenses)

- Multi core, multi cpu
- Accuracy driven
- More accurate than Berkeley (they focus on PLL)
- FineSim from Magma
- XA from Synopsys
- Developed in Grenoble, all new kernel, native MT
- Average of 2.5X faster than Eldo at same accuracy, up to 20x faster
- Input netlists: Eldo, HSPICE
- Some analysis missing in Premier and will be released in next 12 months
- DAC Session at 9AM on Tuesday AM

ADiT – Fast SPICE simulator

- Analog blocks up to 50 Million devices
- Adding new capabilities
- MediaTek standardized on ADiT
- Similar to other Fast SPICE tools
- Macro tuning capability and new partitioning in development

Questa ADMS – Single kernel AMS simulator

- Number one or two market share per EDAC, Gary Smith EDA
- Close to Cadence in market share

Grenoble – Eldo/Eldo Premier R&D
Taiwan – ADiT team/Design Kits
Armenia – CICD R&D
Cairo – models, PDK
Fremont – Division Headquarters
Wilsonville – Custom IC Design R&D
Austin – Custom Router R&D

Innovate In IC physical design, stay close to silicon design.

Technical Advisory Board – multiple initiatives
- Quarterly meetings
Simulators – all work within Cadence Virtuoso (Artist Link)

Analog within Intel microprocessors

Challenges
- Variability (Physical, Electrical)
- Design Risk, AMS is 75% of the risk for failure and cost for design and verification
- Need MS verification (SPICE, HDL, Analog HDL, RTL)
- Questa AMS (Analog Real Number modeling)

Questa ADMS – C/C++, Matlab, VHDL-AMS, …

IC Station (Version 9) – New name is: Pyxis Custom IC Platform (Version 10)

Pyxis – OA database compliant (available now)
- OA native for some functions
- Schematics, Layout, Floorplanning
- Launch simulators
- Concurrent design, multiple designers can edit in the sam cell at the same time
- Custom router
- Multiple designers can edit in the same cell at the same time
- Interface with Clio Soft
- Can be used on LAN, not so tested on WAN yet
- Custom Router (Native OA), easily go back and forth
o Transistor, Cell, Block, Chip, Proven (Used at Marvell) [not related to Olympus – big digital, different division]
o Interactive or batch routing
o Uses Calibre RealTime deck, good integration

Design Kits – founding member of IPL
- Part of Open PDK
- Can help to translate Development Kit formats
- Pcell translator: Robust, accurate, fast (1 foundry, 1 customer using it too)
- Create new PDK’s in a few weeks, able to QA libraries quickly

Summary
Mentor updates their tools for IC layout through the Pyxis acquisition and enhances circuit simulation with a speedier Eldo Premier. AMS co-simulation between HDL and SPICE simulators is a strong point for Mentor.
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