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Best #48DAC Trip Report Gets an iPAD2


Staff member
Post your #48DAC trip reports here. Best trip report wins an iPad2.

Views, replies, ratings (stars), and SemiWiki Staff votes gets you there. This thread will close June 30th.

View attachment 1250View attachment 1251

Good luck and have a great #48DAC!!!!!!!!!

2/9/11 Update:

48th Design Automation Conference: Double Digit Increase in Attendance
Preliminary attendance figures for the 48th DAC break down as follows:
*Total full conference and exhibition: 1,746
*Total exhibit-only attendees: 2,006 (up 13.5% compared to 2010)
*Booth staff: 2,598
*Total attendees: 6,350

204 companies exhibited on the conference floor in 2011, up from 193 in 2010. 29 of these companies were exhibiting at DAC for the first time. Exciting new networking opportunities abounded during the very well attended evening cocktail receptions and around poster sessions. 400 registered tutorial attendees signed up for the new 2-hour, short-course tutorial format.

<script type="text/javascript" src=""></script><script type="in/share"></script>
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I won an iPad from SemiWiki at DAC - Thanks you!!

It was the highlight of an otherwise boring DAC.
Hi Daniel, it was nice meeting you at DAC. Thank you for the iPad2. My wife already took it. :-(

I was only at DAC for two days but here is my impression: Much less people than last year. Some new vendors but no big announcements. DAC is good to get demos and meet vendor people that you read papers from and see on email. The sessions and discussions on 20nm were pretty good. It is nice to see what is coming. Apache had a good presentation and demo on power analysis. Power is the main thing we struggle with today. There was more information on 3D IC this year. I see 3D IC as a good technology for 20nm. Process variation is also big for us. Thank you for pointing me to the Solido presentation at the TSMC booth. I also got a demo. Very interesting software for 28nm.

I did go to the Denali party and saw some strange things:

John Cooley in a Magma shirt?

You talking to the Cadence CEO?

The Mentor CEO?

Some very bad Karaoke!

People taking pictures in costumes with models. These guys must be single or have more tolerant wives than mine!

I will try and add more later. Thank you again for the iPad. Very generous of you.
I saw Dan Nenni talking to Mentor and Cadence CEOs at the same time at the Denali party. I will start the Cadence/Mentor merger rumor right now.

I also got a SemiWiki iPad2. I'm not an Apple fanboy but I like it.

DAC report is this:

The vendor booth shows are stupid. Why do they waste our precious license fees on this nonsense? You know who you are. One company had a magician who only made their money disappear. The girls with big fake boobs at the Denali party? Really? Good thing I did not bring my wife because she would have slapped me for staring. I did appreciate the Mentor beer and wine at the end of the day. The Oasys smoothies were great! I have no idea what they do but it was a great drink.

The Pavilion presentations I saw were mostly self serving. Always a marketing pitch. The Jim Hogan panel Dan did was like this. The PDK panel Dan did was pretty good. 3D extraction was good. The best panel was 3D IC. The worst panel was Women in Engineering. Why? Seriously? Why?

Technical sessions were very good. I will compliment the Mentor people. They had the best vendor paper content. Calibre is still the best product for DRC/DFM and new things are coming that impressed me.

I was most interested to see 3D IC tools and support. TSMC had impressive silicon examples of 3D technology with Xilinx. Altera might be losing the 3D IC race? The 3D IC tutorial was excellent. This is the most exciting technology at DAC.

For the best booth I think GlobalFoundries. They actually had process engineers to talk to. I had a DRC+ discussion with one of the engineers on the development team. Impressive technology. Impressive people.

For the worst booth I think IC Manage. A Ferrari surrounded by stripper like girls? Someone is over compensating here. What a colossal waste of licensing fees. IC Manage customers should be pissed!

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I got an iPad also but have not opened it yet. Dan looks like Robin Williams on steroids. Hahahahahaha! I will write more later. I was a good show this time.
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DAC, San Diego and iPad2


Thanks for the iPad. Getting it setup with various free apps. Great game changer that will radically alter business computing (still need to play with Office on cloud or alternative apps). But given usefulness and instant access/turn on. It will disrupt laptop/netbook sales

San Diego is a great town to visit. Plenty of tourist's attractions, "good weather", shopping, restaurants, etc. But really not good for DAC. Too many firms in Bay Area that either attend or can be added as easy hour mtgs without additional travel. Granted a short hour flight North, but still the hassle of airports, security as well multiple airfare costs. Bay Area is good for international as well as national high tech business men/women. I cannot remember a high attendance in SD for any DAC.

From my understanding, this will be the last DAC in SD. Either SF/LA in a rotation with maybe an Austin side trip in 2014(?) due to not finding a convention site. Austin is a great city also but may have similar issues (this was a comment from an Austinite that attended this year's DAC).

<!--[if gte mso 9]><xml> <w:WordDocument> <w:View>Normal</w:View> <w:Zoom>0</w:Zoom> <w:Compatibility> <w:BreakWrappedTables/> <w:SnapToGridInCell/> <w:WrapTextWithPunct/> <w:UseAsianBreakRules/> </w:Compatibility> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman";} </style> <![endif]--> <!--[if gte mso 9]><xml> <w:WordDocument> <w:View>Normal</w:View> <w:Zoom>0</w:Zoom> <w:Compatibility> <w:BreakWrappedTables/> <w:SnapToGridInCell/> <w:WrapTextWithPunct/> <w:UseAsianBreakRules/> </w:Compatibility> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if !mso]><object classid="clsid:38481807-CA0E-42D2-BF39-B33AF135CC4D" id=ieooui></object> <style> st1\:*{behavior:url(#ieooui) } </style> <![endif]--><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman";} </style> <![endif]--> Here are some comments about the recent DAC48 conference in 5 parts:

(I) DAC conference logistics

a) the technical sessions

DAC changed the technical paper sessions substantially. Most technical papers were reduced from 30 minutes (25minutes, plus 5 minutes for questions) to 15 minutes (12 minutes, plus 3 minutes for questions). After the presentations, the rest of the session time slot was allocated to poster discussions just outside the conference room with the authors.

(Invited papers were typically kept at 30 minutes, but the regular submissions were truncated.)

I surveyed some colleagues and friends, asking what they thought of the new format…

“I liked it… it really makes the authors focus on the key aspects of their work… and, I can quickly decide whether or not to read the conference paper in the proceedings and talk to the author at the poster session.”

“I didn’t like it… some topics really required more time to provide enough material to understand the technical work being presented.”

Personally, I didn’t really care for it… In the past, DAC accepted “short papers”, where the technical review committee accepted the paper, but felt that it did not require a full session. Forcing all papers to fit within this format resulted in some authors to really ‘fly through’ their presentation, flipping through the PowerPoint slides at a fast pace, too fast to read. Or, authors would skip slides altogether, if they got the ‘yellow warning light‘, indicating just a couple of minutes remaining.

When papers were on a 30 minute schedule, it was typically possible to move between sessions, to catch different papers in different conference rooms… the 5 minutes for questions usually allowed attendees to sneak out of one room and into another between papers. On this year’s 15 minute schedule, attending papers from different, concurrent sessions was much more difficult.

And, in many cases, the authors didn’t really put much effort into their posters, to provide more detail on their work -- most were simply hard copies of their PowerPoint charts tacked up on the bulletin board, one page after the other.

One advantage of this new format was that it was possible to walk past the poster boards for all technical sessions held at the same time. I perused the slides for papers that I was interested in, but couldn’t attend.

Maybe there’s a way to support more “long papers” for more complex topics, and still have the authors post their presentation materials.

I would encourage DAC48 attendees to contact the organizing committee with your feedback on the format, favorable or unfavorable.

One complaint I would have is that there was NEVER ENOUGH COFFEE during the session breaks! Inevitably, the coffee urns were empty just a few minutes into the break.

At previous DAC conferences, the ‘tutorial’ sessions were held on (either) Sunday or Friday, so as not to overlap the regular conference. This year, the tutorials were moved to Monday, and reduced substantially in length, enabling attendance at up to 3 tutorials in one day. I guess it’s indicative of how the industry may be changing -- several tutorials were related to coding Android and iPhone apps… just what our industry needs, more ’Angry Birds’.

b) the social hour at the end of each day

I would like to complement the DAC conference organizers on the social hour each evening. It was an opportunity to meet colleagues, ask “what did you see on the vendor exhibit floor worth visiting?”, and enjoy snacks and drinks. The Wednesday social hour also provided another poster session, for papers accepted as “posters only” -- these were valuable additions to the technical part of the conference.

c) the vendor exhibits

The EDA vendor exhibit floor was pretty consistent with previous conferences. As others have already commented, the tendency for EDA vendors to hire professional models and actors to front their exhibit booth is a little unusual for a ‘geek” audience, but it is what it is.

The exhibit floor area had a small “Pavilion” presentation stage, where unique panels and presentations were scheduled. The theme of these presentations were of primary interest to the exhibit floor attendees, rather than the technical conference participants. One complaint was that this Pavilion stage was not large enough (lots of standing around, blocking the aisles); and, the acoustics were loud, so that it was difficult to have a conversation in a nearby vendor exhibit.

The first Pavilion presentation was EDA consultant Gary Smith providing a “what to see on the floor?” summary, categorized by specialization. Gary’s summary was comprehensive, but he did make a forecast that drew snickers from the audience. The total revenue for the EDA industry has pretty much been ‘stuck’ on ~$4B for several years. (As Cadence CEO Joe Costello once described it, “The EDA vendors are all crowded around a dog food bowl, fighting with each other to get a larger share… what we need to do grow the size of the bowl.”)

Gary predicted that this revenue total could grow to ~$5B-$6B by 2015, driven by the increasing focus on system-level design/verification tools, and the EDA cost of rather disruptive technology transitions to 28nm and 20nm. There was definitely (nervous) laughter from the audience at this forecast.

I sure don’t see a 25%+ increase in EDA budgets getting approved anytime soon. Yes, there are new product features required to address DFM and lithographic characteristics of new process technologies (e.g., double patterning-aware routing algorithms). Most EDA customers are on a license lease, with some flexibility in ‘re-mixing‘ the license configuration on a periodic basis. Most customers will no doubt try to work more efficiently within their current lease + re-mix agreement, rather than absorb a substantial increase in current EDA expense.

DAC49 (2012) will once again be in San Francisco, at the Moscone Center. I understand that DAC50 (2013) will be in Austin TX, at their (relatively) new Convention Center downtown.

Well, so much for the conference logistics… on to the rest of the conference…
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<!--[if gte mso 9]><xml> <w:WordDocument> <w:View>Normal</w:View> <w:Zoom>0</w:Zoom> <w:Compatibility> <w:BreakWrappedTables/> <w:SnapToGridInCell/> <w:WrapTextWithPunct/> <w:UseAsianBreakRules/> </w:Compatibility> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman";} </style> <![endif]--> (II) the EDA vendor exhibit floor

As others have commented, there really wasn’t any “WOW!” factor on the exhibit floor… a new product announcement that captured everyone’s interest.

An interesting observation each year is: ‘what companies increased their exhibit booth space, which reduced their space, and which skipped DAC this year altogether?’

Clearly, this was the year of “two foundries” -- TSMC and GLOBALFOUNDRIES -- who both had large booth space (and encouraged EDA vendor ‘partners’ to share the space). Other foundries that have been aggressively exhibiting at DAC were much reduced (IBM) or absent altogether (UMC). A few years ago, when the Xbox360, PS/3, and Wii were all ‘new’, IBM Microelectronics had a huge presence at DAC, using these products as examples of their foundry and ASIC engineering services -- the IBM booth this year was tiny, in comparison, and had little or no ‘pizzazz‘. (I didn’t stop by the Samsung booth -- but, the TSMC and GF exhibits were predominant, compared to the smaller Samsung space.)

On several occasions, I heard TSMC representatives indicate the number of 28nm tapeouts they have received in 2011... I didn’t see comparable tapeout statistics from GF, although clearly they are focused on 28nm design readiness, as well.

Also, noticeably diminished in presence were the engineering workstation hardware vendors. In previous years, demonstrations of the latest desktop hardware was a major facet of the EDA exhibit floor… this year, hardly at all. (I didn’t stop by the H-P booth, about the only hardware vendor in attendance…)

Maybe the reduced engineering workstation dependence foretells a change in computing environment ahead -- perhaps there will indeed be something to the new, proposed operational model: ‘keep your design engineering data in the cloud, not in expensive server farms or unreliable desktop hardware.’ I sure don’t see my engineering management letting someone else look after their proprietary design data anytime soon.

On the ‘front-end’, there are still lots of smaller companies looking to offer design and verification aids, in this era of “assertion-based verification”. Simulation acceleration and (FPGA-based) emulation hardware for verification is still an active industry -- the emulation hardware vendors continue to update their boards with the latest generation of FPGA modules. Vendors with formal model provers and equivalency products are also prevalent. More efficient methods for testcase generation and (IP standard) interface monitor generation are still a vendor emphasis. Yet, the age-old question, ’How much verification is enough, before tapeout?’ remains unsolved.

In the ’physical design’ composition area, the EDA vendors are clearly driven by the foundries to improve their routing algorithms, to incorporate more ‘DFM- and litho-aware features’. (“By 3Q2011, we will have qualified several routers in place for 20nm”, according to TSMC… more on that topic in the Technical Sessions review.)

There was one dichotomy evident in physical design and optimization, especially for analog/mixed-signal IP blocks. Cadence showed their ‘parasitic-aware design’ flow, focused on getting (near-production quality) layouts generated from Virtuoso schematics, incorporating designer-provided constraints. Their goal was to get into layout and parasitic extraction as quickly as possible, to ensure that layout-dependent parasitic effects were included in circuit simulations… however, iterative design optimization with this method is tricky, at best. Others took a different approach, focusing on Design of Experiments techniques to apply statistical sensitivity analysis to schematic netlists to get to an optimization solution, prior to layout generation and (ideally) avoiding numerous layout iterations -- however, the means by which layout-dependent effects are included in this initial optimization analysis was less clear.

Still lots of EDA vendor ‘boasting’ about who has the most efficient Spice simulation (and accelerated circuit simulation) products… which also invoked the mental picture of the dogs around the dog food bowl…

It was interesting to see ‘IC Manage’ with such a large exhibit space… perhaps, they are gaining traction with their products focused on improved design configuration and version management features, as compared to the ‘built-in’ design library managers within the large EDA vendor ‘cockpit‘ products.

I didn’t spend any time delving into more esoteric technologies:

a) EDA vendor companies supporting physical design and analysis of Through-Silicon Via (TSV), or, “3D packaging” ;
b) IP providers (well, there’s ARM, and everyone else J)
c) ElectroMagnetic simulation products for RF and package analysis (the other “EM“ J);
d) DFT tools

And, finally, I felt a little sorry for the poor models at the BeeCube (FPGA prototyping products) exhibit space, who had to wear the bumblebee costumes (complete with wings and antennae).
<!--[if gte mso 9]><xml> <w:WordDocument> <w:View>Normal</w:View> <w:Zoom>0</w:Zoom> <w:Compatibility> <w:BreakWrappedTables/> <w:SnapToGridInCell/> <w:WrapTextWithPunct/> <w:UseAsianBreakRules/> </w:Compatibility> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman";} </style> <![endif]--> (III) Technical Sessions

The following comments are obviously from only a very small sample of the technical sessions… I’ve got my list of conference papers to read, but these comments are based on just the presentations and posters.

There were several quotes that are worth repeating…

1) “System Verilog Assertions (SVA) are still fraught with peril…”
(from Intel, head of the SVA standards committee)

He had several illustrations of where SVA + Verilog semantics work together in unusual ways. The easiest example to grasp was the ‘short-circuit evaluation’ present in Verilog simulators:

assign a = b && f(x, y, z) ;

If signal ‘b’ = 1’b0, Verilog semantics says the expression result is definite, and evaluation of the rest of the expression can be short-circuited. However, the function ‘f’ may itself contain an embedded assertion, checking the values of its input signal list -- that assertion may never get evaluated, and an error in signal behavior missed.

Intel developed their own ‘SVA linter’ and rules to try to look for SVA evaluation issues.

2) “Is Synthesis Robust?”

This was the provocative title of a paper from UC-Berkeley, where the students undertook a simple, but enlightening experiment.

Take a (large) RTL model, and synthesize it to user-provided timing constraints. Then, make trivial (non-functional) changes to the model -- e.g., replace logic expressions with DeMorgan equivalents, change the order of clauses in if/then/else statements -- and re-synthesize.

Naively, you would expect that these non-functional changes would result in no changes in the synthesized results… however, the students found significant differences in many of their experiments.

So, “is synthesis indeed not robust?” J Well, IMHO, their result simply reinforce the point that after initial logic optimizations, the technology mapping and timing optimization algorithms are very local in scope -- the localized structure of the mapped logic network will indeed influence the final results.

3) “no such thing as a typical-typical memory…”

One technical paper reviewed corner-based simulation analysis, and how to optimize the number of simulations needed to demonstrate design functionality over a wide range of process variations. The presenter went pretty quickly, but the proceedings paper is certainly worth a read.)

The memorable quote came while discussing those companies that do a nFET/pFET ‘typical/typical’ process corner (at low supply and high temp). The presenter stated that this is not a valid design point, due to the magnitude of intra-die process variations:

“Just about all critical timing paths involve a memory access… and, with the intra-die variations present, there simply is no such thing as a ‘typical/typical’ memory…”

One thing was clear, throughout many of the sessions… modeling and analyzing design data with statistical process variability will become increasing important.

4) “Designers will need to know about double-patterned layers…” “No, they won’t…”

Several academic papers focused on “coloring algorithms” -- the method by which the layout data on a double-patterned mask layer is divided and allocated to the “A” and “B” mask subsets. Other researchers focused on statistical variation modeling and analysis issues, associated with the A-to-B mask overlay tolerance between shapes on the same layer.

A separate ‘panel session’ addressed the implications of DP layers on the design process… with some real controversy (as opposed to most, somewhat bland, panel session topics).

“Designers will need to know what mask subset assignments are made to specific layouts… especially mixed-signal designers who are concerned about symmetry and centroid layout styles.” (design rep)

“Our process technology design rules will guarantee that the mask data shop will be able to successfully assign data to the A and B subsets… designers won’t have to know anything about DP specifics, if they pass our DRC rules.” (foundry rep)

I think the verdict is still ‘up in the air’ on this one… surprisingly, no AMS designers in the audience expressed an opinion, during the Q&A session after the panelists’ position statements.

5) “Foundries will be buying lots of EUV exposure systems in 2013...”

There was a ‘futuristic’ panel on the upcoming 14nm process node… Although the technical content of their presentations was a little light, there were some interesting conjectures:

“The foundry industry will indeed have made the transition from 193nm to Extreme UV as an exposure source by 2014, to enable 14nm production… all the discussion about double-patterning to support 193nm tools will have become moot.”

“No, foundries will try to push ArF laser exposure with MORE double-patterning for 14nm… and will defer the expense for EUV to 10nm… and, will keep ArF exposure as a back-up, in case EUV systems at that time cannot deliver the throughput or are cost-prohibitive.”

And, to be sure, the FinFET (3D) device structure vs. UltraThinBody (UTB) SOI device structure at 14nm remained an open question. (Several comments were made on the ‘remarkable’ announcement by Intel to push FinFET’s into production in 2012 at the 22/20nm node.)
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<!--[if gte mso 9]><xml> <w:WordDocument> <w:View>Normal</w:View> <w:Zoom>0</w:Zoom> <w:Compatibility> <w:BreakWrappedTables/> <w:SnapToGridInCell/> <w:WrapTextWithPunct/> <w:UseAsianBreakRules/> </w:Compatibility> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman";} </style> <![endif]--> (IV) Keynotes

The keynote sessions were an unusual collection.

Steve “The Woz” Wozniak provided recollections of the early days of Apple, and his design work on the Apple II. There wasn’t much directly related to our industry, other than it often takes perseverance and determination to get past the hurdles to see a concept through to fruition… or, in the case of Apple, to leave H-P and start your own endeavor. I struggled to see how his efforts on DWTS were pertinent to the conference, but it was intended to be an informal chat with The Woz, I guess.

The other keynotes highlighted: a) the increasing emphasis on low-power embedded core hardware and firmware for emerging market products (personal mobility, automotive, medical), and b) the increasing appeal of Electronic System Level (ESL) design methods to accelerate hardware/software co-design. In the latter case, the presenter praised the EDA industry for the investment in high-level synthesis (HLS) and sequential equivalency tools; however, the presenter acknowledged the ‘elephant in the room’ -- design engineering changes made after HLS are very, very difficult to represent back into the ESL model in a provably correct manner.

(V) Summary

So, to net it out… If you were able to attend, you saw a slightly different ‘flavor’ to the conference, especially the technical sessions… however, it would be hard to identify the “Wow!” factors.

If you weren’t able to attend, I’d still encourage you to review the list of exhibitors and read their summaries:

As the ASIC/SoC industry moves from 40nm to 28nm as the ‘sweet spot’ for new designs over the next two years, I don’t foresee major changes in design methods and tools… (unless someone solves the ‘how much verification is enough?’ question)

So, the next DAC could be more of the same... or, perhaps not...

DAC49 in SF could start to introduce the requirements for designing at the 22/20nm node (much more stringent DFM and litho requirements), which may or may not be disruptive to design methodologies, depending upon who you believe. And, there could be an early look at the extremely disruptive transition to 14nm devices, whether they be FinFET’s or Ultra-Thin Body SOI FET’s.

I’d encourage the SemiWiki readers to make your DAC49 plans now…

Hope you found this (somewhat) interesting…
<!--[if gte mso 9]><xml> <w:WordDocument> <w:View>Normal</w:View> <w:Zoom>0</w:Zoom> <w:Compatibility> <w:BreakWrappedTables/> <w:SnapToGridInCell/> <w:WrapTextWithPunct/> <w:UseAsianBreakRules/> </w:Compatibility> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if !mso]><object classid="clsid:38481807-CA0E-42D2-BF39-B33AF135CC4D" id=ieooui></object> <style> st1\:*{behavior:url(#ieooui) } </style> <![endif]--><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman";} </style> <![endif]--> My #48DAC trip report

This was my 28<sup>th</sup> DAC, the first being 1984 @ Albuquerque New Mexico. The 1985 DAC was in Las Vegas to which I brought my beautiful new bride. She was expecting much more professional behavior but EDA was a bit crazy back then and Las Vegas is Las Vegas. Since then I have been to New Orleans twice, Orlando, Dallas, Las Vegas a couple more times, San Francisco, Los Angeles a bunch of times and of course San Diego.

Funny story:
To promote SemiWiki I hired a young woman to scan conference badges from an agency called Sensational Events. My wife later noticed that the Agency name was Sinsational Events! I swear on my life I thought it said Sensational!!!! The young lady they sent was very professional and a great fit for #48DAC if you think about it. She scanned a total of 723 conference badges, 200+ have already signed up for SemiWiki. Some people she approached said they did not want an iPad2, very strange. The people who won SemiWiki iPad2s however were very appreciative.

My oldest son Ryan, (SemiWiki developer) accompanied me this year. One of the reasons I started SemiWiki was to spend more time with him and it has worked out great. Ryan spent most of his time talking to the Sinsational girl and playing poker at the Cliosoft booth. I couldn’t be prouder!

Flying on United sucked! Our flight home was delayed for hours so there we sat at the airport. Luckily they have free Wifi, Ryan and I are never bored when there is free wifi! He is a great guy, PARENTING WIN! The United Airlines staff was not great, I really hate flying United. Unfortunately my next trip to Taiwan is on United via Japan so there is more pain to come. The ticket price was much less than my favorite EVA so there you have it.

Party Stories:
John Bruggeman personally invited me to the Denali party with VIP bracelets. As I have written before, John is a great guy. You could power a city with John’s energy.

At the Denali party I was talking to Randy Caplan, Silicon Creations cofounder, when my favorite EDA CEO joined in. Before I could introduce them Randy asked Wally who he worked for. Wally said Mentor and Randy asked what he did at Mentor. Wally said CEO. Randy then asked how long he has been CEO of Mentor. Wally answered 19 years. Sorry Randy, that was funny, especially since you just bought Calibre. Lip-Bu Tan, Cadence CEO joined our conversation as well, a very friendly guy!

Before the Denali Party was the Synopsys dinner at Flemmings. Great food, great people, even Aart attended this year. Daniel Payne got a seat next to Aart so hopefully he will blog about it. I sat next to Ed Lechner, the Director of Marketing for the Synopsys AMS product. Ed and I plotted against the Virtuoso monopoly through dessert.

Across the restaurant was a table full of Cadence and TSMC people. Hopefully an iPDK support agreement was finalized because if Cadence does not FULLY support TSMC iPDK I will continue to push Cadence customers away from Virtuoso. DOWN WITH MONOPOLIES! KILL SKILL! KILL SKILL! KILL SKILL!

The Mentor dinner on Monday night was very good. There were great views of Coronado, great food, and great conversations with Mentor’s top customers. Mentor is a class act and I look forward to them having a great year. I also like Mentor’s booth at DAC. Very modest in front, very deep with meeting rooms, nothing like the Cadence and Synopsys ego booths. Carl Icahn should be happy. Mentor also provided free beer and wine at the end of each day, a class act.

Since I was on the DAC floor promoting SemiWiki full time I missed the sessions sorry to say. The best DAC coverage comes again from Richard Goering’s Industry Insights blog which can be found HERE. Richard is also a class act even though he is shilling for Cadence.

You can also catch the Woz’s DAC keynote on Youtube. It’s an interview format with Mike Cassidy from the San Jose Mercury News. You can find the four part video series on Mike Demler’s new site EEDaily HERE.

Most Exciting New Technology:
Hands down George Janac’s ChipPath. ChipPath is the creator of a new Semiconductor IP Centric Design Approach focused on design simplicity, software integration, semiconductor IP integration, and subsystem and analog IP. Definitely check it out!

Honorable Mentions
TSMC and GlobalFoundries had the best booths. Talking to process people and their design ecosystem partners held the most value. You get to see what the future is and learn from their experience. Samsung was there as well but they won’t talk about tape-outs, test chips, capacity, or other stuff that you need to know. They have not learned how to be a foundry yet.
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Nimbic (formerly Physware) - 3D Field Solver in the Cloud or Desktop

I met with Bala Vishwanath, CMO at Nimbic on Monday morning. They had just announced a $6.9M round of venture capital which is something that you rarely hear about in EDA these days, especially during a slow economic recovery.
View attachment 1259


Physware – served the package and board markets, co-design challenges (can add IC noise sources). As complexity increased customers wanted more capacity in compute, how about unlimited capacity using the cloud ?

What's New
Parallelization – both distributed and multi-core. The cloud can handle this configuration, always accurate with full 3D field solving. Product name is nCloud.

Still have enterprise tools on your desktop or on a compute farm.

Cloud – can pay by the hour, or mixed with enterprise.
SaaS – pay by the hour.

Pricing models – by the hour, subscribe annually on the cloud. If Enterprise is 100% , then the could would be double the cores to 8 for the same price.

Security – Even Nimbic cannot see the data. Each HW is separated per client, secure channels used with RSA key pairs in transit (data at rest, on dedicated HW, encrypted Disk, key lives in the instance, all the virtualized layers come from Amazon, then we add on top of that).

Private Cloud – sure that could be used. The Amazon API has been broadly used.
Cloud machines – they reside in Virginia, but could be located anywhere they want.
Managers – can setup monthly budgets to not exceed
Venture financing - $6.9M in Series B, existing Investor and one new one added.

Runing Ubuntu Linux in the cloud right now.

Plan to add more of a flow management system.

How long is your data there? Not archival duration. Results stay there as long as you want. Don’t consider it archival. S3 = Simple Storage Service.
Chile, development (Founder from Chile)

Partnership release with Amazon to be coming.
Nimbic GUI (nWave) – running on Windows, 10 Amazon machines with 8 cores each. GUI also runs on Linux.

Nimbic re-invents itself by offering a 3D Field solver in the Cloud and securing new venture funding. The trend of EDA companies offering their tools in the Cloud continues at DAC 2011.
FineSIM adds RF Analysis plus new Tcl Circuit Checks

At DAC I spent time in the Magma FineSIM demo suite on Monday morning.

Greg Curtis – Product Director, Custom Design Business Unit
View attachment 1261
- Talus for Digital Design
- FineSim does: SPICE, FastSPICE, Characterization
- Flows Demoed at DAC: High Performance Core, SOC, ASIC/ASSP, AMS, Memory
- What’s New in FineSim?
o RF
o TCL circuit checks
- ADC design trends
o Parasitics dominate performance now
o Sensitivity to noise and cross talk
o Operating at low power
o Requires more SPICE, more corners, more analysis
- Cell phone trends
o 10+ radios per phone
o Maximum battery life
- FineSim SPICE
o Multi-cpu and multi-machine capability
o Standard netlist inputs (HPSICE, ELdo, Spectre)
o ER and IR drop analysis
o Co-simulate with Verilog and VHDL
o New:
 Tcl based circuit checks (interactive simulation)
• Customized check that you write to check currents, voltages, timing
• Set breakpoints
• Demo: find all outputs above 2.6V
• Demo: At 5th rising edge, wait 25ns, capture signals, check sum of currents, trigger if >50uA used
• Could write Tcl code to calculate the jitter of a PLL real time during simulation
• Technology could traverse a netlist similar to Calibre PERC, but not there yet
 RF Analysis (Harmonic Balance, Periodic AC Analysis, Periodic Noise, Periodic Transfer, Oscillator Phase Noise)
• Multi-CPU capability
• Due in November 2011
• Beta in September 2011
• A new option to FineSim SPICE
• Demo of a 9 stage ring oscillator
o One CPU run first, 25 seconds
o Four CPUs run next, 12 seconds
o FineWave used to show the waveform results
o AC wave, phase noise plot shown
 EM/IR Analysis
• Titan is being used for EM/IR Analysis
• Demo of NAND gates in a layout and schematic
• Titan uses the Analog Simulation Environment (AVE)
• EM/IR analysis results viewed on top of the layout using color codes, layout zoomed in when clicking on a specific EM/IR result
• Capacity is a few million MOS devices
o 1.5X Faster than Berkeley (PLL)
o 1.4X faster than Cadence APS (Sigma Delta Modulator)
o 5X faster than Eldo
- FineSim PRO
o Multi-rate engine, hierarchical processing (but not hierarchical simulation)
o Same features as FineSim HSPICE
o Capacity example had only 4.6M devices
o 7.9X to 16X faster than NanoSim, Hsim,XA (under 2M MOS devices)
- 2011.04 release versus 2010.08
o 1CPU, 7.5% less memory. 1.23X run time improvement
Foundry Support
- TSMC, GlobalFoundries, TowerJazz, Lfoundry

Customer Usage:
- 12 of top 20 Semiconductor companies using FineSIM
- Analog Bits, 10X speed up wit FineSim
- ESNUG user: 3X to 10X over HSPICE

Anand Ganesan – Senior Product Engineer (demonstrations)

FineSIM catches up to HSPICE, Eldo and Spectre in simulating RF circuits.

The Tcl Circuit Check looks similar to the technology in Mentor's Calibre PERC. Let's see if they create a product to detect ESD best practices like PERC does.
IPL Alliance focuses on iPDKs and Analog Constraints

Lunch time Monday at DAC and I learned about what's new at the IPL Alliance in 2011.

IPL Sponsors: Magma, Mentor Graphics, Springsoft, Accelicon, Ciranova, Synopsys, TSMC, TowerJazz, Jedat, Tanner EDA

Two major projects:
1) iPDKS
2) Analog Constraints

- Reduce development costs for library development
- Standardize to be efficient

New Members:
-ST, Xilinx, Dongbu

- June 2011: IPL Constraint 1.0 Available

IPL 1.0
- Comes with a 90nm reference iPDK

IPL Constraint 1.0
- New emerging standard for Constraints

Rich Morris – Marketing Manager at SpringSoft, Chairman of Constraint Working Group at IPL Alliance
- IPL Constraing 1.0 Standard (single unified set of interoperable constraints)
- Active members: Altera, Ciranova, Pulsic, SpringSOft, Synopsys, TSMC
- Constraints: Design Rules (what not to do)
- PDKs have lots of constraints
- OA has 145 foundry constraints
- IPL is focused on design constraints, not foundry constraints, typically analog and custom design

What type of constraints?
- Communication between schematic entry design and IC layout implementation
- Enter constraints once for entire tool chain, not multiple times
- Today: Constraints for Placement, Routing, Layout editing (All different)
- Open Access: consistent way to store constraints for all design tools
- Text-based constraints can synch with the OA DB

- Define the syntax and schema for open, interoperable design constraints
- Create a single unified set of constraints
- Start with a proof of concept constraint set
- Ask for donations from real users to maximize coverage

- Placement with one tool, routing with another tool

- If I make a constraint how do I know that it is legal or valid?

- Future expansion built in

- Routing: wire width, wire space, preferred direction, net matching
- Placement: Group symmetry, group alignment, …

Publication of Constraints Standard – Coming next

Design Constraint Standard
– using YAML (easy to parse, human readable, open source)

IPL Constraints 2.0
- Planned for end of 2011
- General release in 2012

Steven Chen – Deputy Director at TSMC

TSMC AMS Reference Flow 2.0 & Design Constraint

- 2006: 65nm, Cadence PDK
- 2007: Porting PDK tool by tool
- 2008: Demo TSMC iPDK concept
- 2009 65nm iPDK
- 2010: 28nm iPDK, 40nm, 65nm, 90nm, 130nm, 180nm

AMS Reference Flow 1.0
- An interoperable AMS design flow
AMS Reference Flow 2.0
- DFM and RDR compliance defined
- Design iteration and cycle-time reductions
o Predict and optimize layout style to LDE, RC and IR
- Design for Reliability
o Flag issues early before tapeout
o Layout based, simulation based DFR flows
- EDA tool flow integration of 28nm HP and HPM nodes

AMS Challenges
- At 65nm we see 16% LDE impact, 40nm a 22% LDE impact, at 28nm 28% LDE impacts
- Cause much simulation and iterations to converge

AMS Flow
- Constraint driven physical effects (LDE, RC) aware flow defined
- Pre-layout: LDE budgeting, custom wire load emulation
- Covers: Schematic Driven Layout, Analog P&R

Electric Design Constraints
- Device: Idsat self-degradation
- Parasitic
- Power
- Device costs
- Parasitic costs
- Power costs
- Device matching
- Parasitic matching
- Power matching

Pre-layout flow
- Use the TSMC iPDK
- LDE budgeting (pass constraints to each layout tool, RC extractor)
- Custom wireload estimation
- An LDE API is provided by TSMC
- RC Extraction API: Between extraction tool and layout editor
- TSMC provides an LDE constraint checker

Demo Case Study
- Old way versus new way showed a reduction in pre/post layout simulations.

Vincent Varo – ST Micro, iPDK and Open PDK

- Common objectives
- ST wants standardization to reduce design and support costs
- Open PDK goal is a single PDK generation flow
- iPDK will enable a single PDK
- Both concepts (iPDK, Open PDK) are complementary efforts

PDK ecosystem today
- Each foundry starts with a PDK
- PDK development team (Device libraries, DRC, LVS, SPICE, PEX)
- Too many versions of PDKs creating a large support efforts

PDK ecosystem goal
- Foundry creates and electronic document with both DRM and device specifications
- A PDK generator creates an automated techfile

- Is creating an Open PDK Standard (OPS) XML file
o Has: Process, libraries, devices, layers, rules
- A Standardized High level EDA tools tech file
o Goes into a PDK Translator
o EDA tools could read the high level tech file directly

New IPL Working Group – connecting Open and Interoperable groups

How do you validate a PDK?

Next steps
- Automation of an iPDK generator
- Interoperable PDK validation
- IPL Adopter Kit

Ofer Tamer – CAD Director at ToawerJazz

iPDK Advantages

Who is TowerJazz?
- Specialty foundry. RF. Image Sensor. Power management. MEMS.
- Processes: .50um to .13um, all AMS

Multi-vendor flows: Cadence, Synopsys, Mentor, Magma, SpringSoft
- Use CiraNova tools for library development
- iPDK tools: Synopsys Custom Designer, Magma Titan, Mentor IC Station, SpringSoft Laker
- Allows PDF development to use a single methodology, not specific to any one EDA vendor format
- PyCells used to create Pcells

TowerJazz AMS Reference Flow
- Live demo today showing Synopsys Custom Designer tools
- Same flow to show tools for: Cadence, Magma, Mentor, Ciranova


Q: IPL is based on OA from Cadence, but where is Cadence support today?
A: TSMC - That’s a tough question. Cadence has been invited to be part of IPL. TSMC has used IPL libraries in Cadence tools just fine. Customers are the drivers to change the mind of Cadence to support and join IPL.

A: TowerJazz does two PDKs: Cadence, IPL. Doubles their development efforts.

A: ST – Develops two PDKs: Cadence, IPL. Want to support just IPL.

Q: What’s the next development from IPL?
A: We’re limited in resources, depend on member resources. Enhance Constraint 1.0 for public release at next DAC.

Q: What about an interoperable Simulation language?
A: Synopsys – we take input from IPL members to sponsor a working group.

Q: Twitter Question.
A: IPL stands for Interoperable PDK Libraries

Cadence continues to promote only their Skill-based PDK while the rest of the industry is adopting iPDK and Open PDK. The message from the speakers today was loud and clear, "Ask your EDA vendors and Foundries to support iPDK".
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Physical IP Group at ARM

After lunch on Monday I met with John Heinlin, Ph.D. – VP Marketing of Physical IP Division

View attachment 1267

Back in the day I knew the founders of Artisan (VLSI Libraries) when we worked together at Silicon Compilers (Mark Templeton, John Malecki, Scott Becker).

View attachment 1282
Q: Do you favor any EDA tools for creating your IP?
A: No, we don’t really endorse a specific EDA vendor tool or flow.

Q: What's new at ARM for 2011?
A: Just started Process Optimization Packs. Linking IP that is tuned for ARM cores.

Artisan – Generic cells. Used to wait for a node to become stable.

ARM – Focused on leading edge cells, now at 28nm nodes. Now doing test chips quite early to tweek and optimize cells, as requirements into the process.

2010 – 32nm last year announced.

2011 – 28nm IP is now ready as soon as announced. TSMC, SMIC, Samsung, IBM, GlobalFoundries (CP), TSMC.

Q: How to reach Power Performance and Area for your design?
A: We have a User Guide on how to get best results.

Q: Any preference for PDKs?
A: Support whatever PDK is available, no preference.

Synopsys – renewed tools agreement for a period of time.

Cell Library – about 1,000 cells to choose from, with about 100 different functions. Simple gates, flip-flops (power saving modes)

Q: What is your royalty model?
A: Royalty Model – same as always, no upfront costs. Foundries pay for library development.

Memory compilers cells – Standard RAMS, then lower VDD RAMs for an extra price. Typically 5 to 7 compilers per node.

Foundries – Some are offering their own libraries.

ARM Artisan IP (re-using)

Memory Compilers – Virage (Synopsys) has a piece of it. ARM invests heavily in these at leading edge nodes. Area efficient nodes too.

SOI – French based (SOISIC), acquired about 5 years ago, used at IBM.

Physical – GP IOs, 40nm Low Power. Will add DDR libraries soon. Have controller, PHy and IO in one piece.

Q: What do you think of Intel's TriGate?
A: FinFET – At 20nm planar CMOS still works, 14nm then FinFET looks viable.

Q: What is success for ARM?
A: Success – We think rich solutions across a wide range of foundries at 28nm now, 20nm soon (test chips with Samsung).

Q: How do you use RDR?
A: RDR – We’ve been dealing that for a few nodes now (20nm needs double patterning). We work closely with foundries for all nodes.

Common Platform – ARM is the IP you get.

Q: Where do I find out more?
A: Visit our SOC Design Community

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HSPICE gets Faster, better Convergence

Hany El Hak – Product Marketing Manager

Frederik Iverson – AE
View attachment 1272
Scott Wetch – HSPICE Architect

HSPICE – 5 years ago convergence was not so good, while 95% of analog circuits today converge out of the box, no options are required.

Synopsys AMS Portfolio – wide range of tools
- Custom Designer: IC schematic and layout tools
- HSPICE – circuit simulation
- CustomSim – full chip circuit simulation
- IC Validator/Star RC – extraction, DRC, LVS

HSPICE – Golden SPICE standard for about 30 years now, the same tool the foundry used to create their cells
- Used in IC, AMS, PCB for SI

Issues – Long run times, could be days to cover all of the corners required, more runs

Improvements in HSPICE – 5X faster than 2007 on a single core, averaged over 100’s of circuits
- Precision Parallel, 7X faster when using 8 cores compared to a single core
- 10X more capacity, about 10 million elements
- New Analysis added: High Frequency, Statistical Eye Diagrams, Transient Noise, Loop Stability
- Convergence, 95% out of the box, no settings required
- Distributed Processing (MC, Corners, Sweeps) – distribute over the network (17X on 20 CPUs)

HSPICE Precision Parallel – run times reduced from days to hours
- Up to 7X faster on 8 cores (use –hpp option)
- PLL runs now reduced to 4 hours instead of days
- PLL example with 7K MOS and RC, 12.5 hours (148 hours, competitor)
- Clock Tree with 10M elements, 7 hours (108 hours, competitor)
- Sigma Delta Converter, 7.7 hours (16 hours, competitor)

HSPICE Distributed Processing – divide and conquer (MC, corners with .ALTER, sweeps)
- 10 CPUs at 8.7X faster
- 20 CPUs at 17.3X faster (some overhead to collect all that data)

Post-layout – selective net back-annotation (use parasitic only where needed)
- Check and find only the active nets for extraction (automatic or manually identified)
- Apply parasitics only to critical nets that are identified

Transient Noise Analysis – Include noise in time domain simulations (about 2X to 3X slower than transient)
- Full nonlinear analysis of noise effects in the time domain
- All devices are taken into account (thermal noise, channel noise, flicker noise)
- Today a single CPU, in September see the parallel version

Custom Designer (Schematics and Layout)
- HSPICE integrated within

Frederick Iverson, demo of Duty Cycle Corrector (40nm node, Used in IP group for USB 3.0, 450 analog designers at SNPS)
- Custom Designer uses OA for a db. Any circuit simulator can be added to Custom Designer.
- Normal simulation is 5 minutes to complete, Precision Parallel completes in about 1 minute
- Command line has Tcl, so it’s easy to save and re-run commands.
- Si2 is showing how to run tools with many languages: Tcl, Perl, Ruby, etc.
- Plot of simulation results shown in WaveView tool, measurement tool to show % duty cycle.
- HSPICE uses one license for two threads, so use it at no extra cost
- Back annotate a full netlist or a partial netlist (used a DSPF file from Star RC)
- Names in HSPICE are the pre-layout names even with back-annotated values
- Transient noise demonstrated, the output does show jitter, wave view shows jitter versus time, histogram shows standard deviation on jitter values

HSPICE has to continually improve in order to stay current with Berkeley DA, Eldo, Spectre and FineSIM circuit simulators.
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QuickCap for IC Extraction at DAC 2011

John and Ralph from Magma gave me an update on QuickCap at DAC on Monday afternoon in their demo suite.
View attachment 1274

John Schritz – Sr AE
Ralph Iverson, Ph. D. (wrote QuickCap)

John Schritz
- Digital Signoff, extraction
- QCP: 2.5D RC for full ASIC designs
- QuickCAP NX: 3D field solver
- QCP:

Demo – 1.5 million instance design, 1.59 million nets, fully P&R, three libraries
- QCP: Gate Level (Star RC competitor)
- QuickCapNX: 3D field solver (Raphael competitor)
- QCP TX: Transistor Level (RC XT competitor)
o 10X faster than Star RC
o 20X faster with multi-corner extraction
o Accuracy: +-2% of QuickCap NX
o TSMC qualified at 28nm
o Inputs: LEF, DEF, GDS II
o Scaling: can add multiple corners using only 20% run time, can be distributed across more boxes
o Capacity: 50M instance designs, memory efficiency
o Accuracy (vs Star RC)
o Example: TSMC 40nm, 38K nets
o 1 corner at 5 hrs, 12 corners at 8.4 hours (27X faster than Star RC), using 3.3GHZ CPU, 148GB and 12 CPUs
o One license per four cores (after that add a multi-core to add up to 32 cores)
o 16 Synopsys licenses for a runtime of 60 minutes, vs 2 licenses in 34 minutes
o ½ the run time, ¾ the HW, 1/8 the licenses (compared to Synopsys with 80% market share)
o 3D on demand (add QuickCap NX), name the nets you want best accuracy on
- Tekton – a STA tool
o Reads SPEFS
o Fast STA in minutes
o Concurrent MM/MC
o Accurate with SPICE integration
- Old flow
o Implement, output a GDS II
o Extract, output SPEF
- New Flow
o Implement
o QCP and Tekton
- QuickCap NX: Industry Golden 3D Field Solver
o Same run time independent on
o Three methods:
 Finite Element (Slowest)
 Boundary Integral (Slow, what Mentor 3D XACT uses)
 QuickCap (Fastest)
o Field-solver accuracy (within 1% of Silicon)
o Good for library characterization, custom, analog
o Flow Inputs: ITF or iRCS from foundary, GDS II layout
o Industry standard solver at IDMs, Foundries
o Edge effects
o Qualified by TSMC
- QCP TX – transistor level extraction
o Millions of transistor capacity
o To be released in 6 months
o For: Custom design, memory, AMS
o CCI – Calibre Connectivity Interface, stress parameters, well proximity
- QCP Demo
o 18 million nets extracted per hour on 8 threads

Star RC (Synopsys) has plenty of competition from Magma, Mentor and Cadence for IC extraction. I also learned more about 3D Field Solvers on Tuesday at the Pavilion Panel session.

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CyberEDA adds a Transistor-Level Debugger

I met with CK Lee, founder of Cyber EDA at his booth on Monday evening in San Diego. Last year I learned about their new SPICE circuit simulator named PCSIM, this year the new product is called ADDS-Debugger.

View attachment 1276


2010 – Announced a debugger

2011 ADDS Debugger – trace at the transistor level your design
- Signal tracing
- Post-layout debug
View attachment 1277
o Tracing – which signal triggered that net that rose or fall?
o Trace back to a Primary input
o Cross-probe between auto-generated Schematic and the waveforms
o Pricing: $50K per year
- ADDS Wave
o Pricing: $2K per year
- PCSim
o Pricing: $25K per year
o Post-layout simulation speed improved, 3X
o True SPICE simulator, flattened
o Compete with HSPICE, SPectre, ELdo

Customers – Ali (Taiwan)
- Extreme DA

Based: Santa Clara, CA

Employees: 10

Next Year: Double revenues

Sales: Direct mostly, some distributors

ADDS Debugger reminded me a lot of what Concept Engineering has been offering for several years now in a transistor-level debugger. What makes this different is that you're inside of a circuit simulation run when you can visualize the netlist as a schematic and see the node voltages and branch currents.

The SPICE circuit simulator market is crowded with many EDA vendors (Synopsys, Mentor, Cadence, Magma, Berkeley, Tanner EDA), so Cyber EDA has to do something special in order to make PCSIM stand out from the crowd (speed, accuracy, capacity, features).

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Monday Night Mentor Networking

View attachment 1280
That's the view we had on Monday night at the Mentor networking and dinner event in San Diego. Simply a stunning view and wonderful company with other editors, bloggers and EDA customers.

On the bus ride over to dinner I sat next to a fellow from CSR and learned a lot more about their radios that power most of the consumer electronics that I use daily.
View attachment 1281

Wally Rhines did make a brief appearance and promised not to talk about products, however we did learn a little about their success in the automotive and embedded markets , plus we even met one of the new board members from Carl Icahn's hostile bid.

The entertainment for the evening was a world-class magician with a degree in Physics that simply defied all the laws of my known universe. The finale with light saber effects was unlike anything I've witnessed before. Great fun, and I have no clue how he did all of those illusions.